71M6543F Maxim, 71M6543F Datasheet - Page 151

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71M6543F

Manufacturer Part Number
71M6543F
Description
The 71M6543F/71M6543H are Teridian's 4th-generation polyphase metering system-on-chips (SoCs) with a 5MHz, 8051-compatible MPU core, low-power real-time clock (RTC) with digital temperature compensation, flash memory, and LCD driver
Manufacturer
Maxim
Datasheet

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6.8.2 71M6543 Analog Pins
Pin types: P = Power, O = Output, I = Input, I/O = Input/Output. The circuit number denotes the equivalent
circuit, as specified in Section 6.8.4.
v1.2
Pin
87
86
68
67
66
65
64
63
84
83
82
88
75
76
VADC10 (VC)
VADC8 (VA)
VADC9 (VB)
IADC0
IADC1
IADC2
IADC3
IADC4
IADC5
IADC6
IADC7
Name
XOUT
VREF
XIN
© 2008–2011 Teridian Semiconductor Corporation
Type
O
O
I
I
I
Table 113: 71M6543 Analog Pins
Circuit
6
6
9
8
Differential or Single-Ended Analog Line Current Sense
Inputs. These pins are voltage inputs to the internal A/D
converter. Typically, they are connected to the outputs of
current sensors. Unused pins must be connected to
V3P3A.
When configured as differential inputs (i.e., by setting the
DIFFx_E control bits, where x = 0, 2, 4, 6) pins are paired to
form differential inputs pairs: IADC0-IADC1, IADC2-IADC3,
IADC4-IADC5, and IADC6-IADC7.
IADC2-IADC3, IADC4-IADC5, and IADC6-IADC7 can be
configured for communication with the 71M6xx3 remote
isolated sensor interface (i.e., by setting the RMTx_E
control bits, where x = 2, 4, 6). When configured as remote
sensor interfaces, these pins form balanced digital pairs for
bidirectional digital communications with a 71M6xx3
remote isolated sensor.
Line Voltage Sense Inputs. These pins are voltage inputs
to the internal A/D converter. Typically, they are connected
to the outputs of resistor dividers. Unused pins must be
connected to V3P3A.
Voltage Reference for the ADC. This pin should be left
unconnected (floating).
Crystal Inputs. A 32 kHz crystal should be connected
across these pins. Typically, a 15 pF capacitor is also
connected from XIN to GNDA and a 10 pF capacitor is
connected from XOUT to GNDA. It is important to
minimize the capacitance between these pins. See the
crystal manufacturer data sheet for details. If an external
clock is used, a 150 mV (p-p) clock signal should be
applied to XIN, and XOUT should be left unconnected.
71M6543F/H and 71M6543G/GH Data Sheet
Function
151

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