ST10R272L STMicroelectronics, ST10R272L Datasheet - Page 61

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ST10R272L

Manufacturer Part Number
ST10R272L
Description
16-BIT Romless MCU WITH MAC UNIT
Manufacturer
STMicroelectronics
Datasheet

Specifications of ST10R272L

Cpu Frequency
0 to 50 MHz
Power
3.3 Volt +/-0.3V

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Parameter
Data hold after RdCS
Data float after RdCS
(with RW-delay)
Data float after RdCS
(no RW-delay)
Address hold after
RdCS, WrCS
Data hold after WrCS
1) Output loading is specified using Figure 13 with CL = 5 pF.
2) This delay assumes that the following bus cycle is a demultiplexed bus cycle and that the
data bus will only be driven externally when the RD or RdCs signal becomes active. RW-
delay and
cycle, refer to equivalent multiplexed AC timing (which are still applicable due to automatic
insertion an idle state (2TCL) when switching from Demultiplexed to Multiplexed Bus Mode.
1 2
1 2
t
A
refer to the following bus cycle. If the following bus cycle is a muxtiplexed bus
Symbol
t
t
t
t
t
51
53
68
55
57
Table 18 Demultiplexed bus
SR
SR
SR
CC
CC
Max CPU Clock 50MHz
min.
0
-5 +
3 +
t
F
t
F
ST10R272L - ELECTRICAL CHARACTERISTICS
max.
13 +
2tA
3 +
2
t
F+ 2tA
t
F +
2
Variable CPU Clock
1/2TCL = 1 to 50 MHz
min.
0
-5 +
TCL - 7 +
t
F
t
F
max.
2TCL - 7
+
TCL - 7
+
t
t
F + 2tA
F + 2tA
2
2
ns
ns
ns
ns
ns
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