ST10R272L STMicroelectronics, ST10R272L Datasheet - Page 48

no-image

ST10R272L

Manufacturer Part Number
ST10R272L
Description
16-BIT Romless MCU WITH MAC UNIT
Manufacturer
STMicroelectronics
Datasheet

Specifications of ST10R272L

Cpu Frequency
0 to 50 MHz
Power
3.3 Volt +/-0.3V

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ST10R272L
Manufacturer:
ST
0
Part Number:
ST10R272LT1
Manufacturer:
PANASONIC
Quantity:
30 000
Part Number:
ST10R272LT1
Manufacturer:
ST
0
Part Number:
ST10R272LT1
Manufacturer:
ST
Quantity:
20 000
Part Number:
ST10R272LT1/TR
Manufacturer:
STMicroelectronics
Quantity:
10 000
Part Number:
ST10R272LT1/TR
Manufacturer:
ST
0
Part Number:
ST10R272LT1VJ022IWC
Manufacturer:
ST
0
Part Number:
ST10R272LT6
Manufacturer:
CYPRESS
Quantity:
1 400
Part Number:
ST10R272LT6
Manufacturer:
ST
Quantity:
20 000
ST10R272L - ELECTRICAL CHARACTERISTICS
Prescaler operation
Set when pins P0.15-13 (P0H.7-5) equal ’001’ during reset, the CPU clock is derived from the
internal oscillator (input clock signal) by a 2:1 prescaler.
The frequency of f
duration of an individual TCL) is defined by the period of the input clock f
The timings listed in the AC characteristics that refer to TCLs therefore can be calculated
using the period of f
Note that if the bit OWDDIS in SYSCON register is cleared, the PLL runs on its free-running
frequency and delivers the clock signal for the Oscillator Watchdog. If bit OWDDIS is set, then
the PLL is switched off.
Direct drive
When pins P0.15-13 (P0H.7-5) equal ’011’ during reset, the on-chip phase locked loop is
disabled and the CPU clock is driven from the internal oscillator with the input clock signal.
The frequency of f
(i.e. the duration of an individual TCL) is defined by the duty cycle of the input clock f
The TCL timing below must be calculated using the minimum possible TCL which can be
calculated by the formula:
For two consecutive TCLs the deviation caused by the duty cycle of f
the duration of 2TCL is always 1/f
only once for timings that require an odd number of TCLs (1,3,...). Timings that require an
even number of TCLs (2,4,...) may use the formula:
48/77
1
0
P0.15-13 (P0H.7-5)
1
0
0
0
1) The maximum depends on the duty cycle of the external clock signal. The maxi-
mum input frequency is 25 MHz when using an external crystal oscillator, but
higher frequencies can be applied with an external clock source.
0
0
1
1
0
0
CPU
0
1
0
1
CPU
XTAL
Table 15 CPU clock generation mechanisms
is half the frequency of f
directly follows the frequency of f
for any TCL.
CPU frequency
f
F
F
F
F
TCL
F
CPU
XTAL
XTAL
XTAL
XTAL
XTAL
min
= f
* 5
* 1
* 1.5
/ 2
* 2.5
XTAL
XTAL
=
1 f
. Therefore, the minimum value TCL
* F
XTAL
External clock
input range 10-
50MHz
2 to 10 MHz
1 to 50 MHz
6.66 to 33.33 MHz
2 to 100 MHz
4 to 20 MHz
XTAL
DC
min
and the high and low time of f
2TCL
DC
XTAL
=
=
so the high and low time of f
duty cycle
1 f
XTAL
Notes
Direct drive
CPU clock via 2:1 prescaler
XTAL
.
XTAL
is compensated so
min
1)
.
has to be used
CPU
XTAL
(i.e. the
CPU
.

Related parts for ST10R272L