ST10R272L STMicroelectronics, ST10R272L Datasheet - Page 20

• Manufacturer Part Number: ST10R272L
• Description: 16-BIT Romless MCU WITH MAC UNIT
• Manufacturer: STMicroelectronics

Specifications of ST10R272L

• Cpu Frequency: 0 to 50 MHz
• Power: 3.3 Volt +/-0.3V

ST10R272L - MULTIPLY-ACCUMULATE UNIT (MAC)
Accumulator shifter
The Accumulator shifter is a parallel shifter with a 40-bit input and a 40-bit output. The source
operand of the shifter is the Accumulator and the possible shifting operations are:
•
•
•
E, SV and SL bits from MSW are affected by Left shifts, therefore if the saturation mechanism
is enabled (MS), the behavior is similar to the one of the arithmetic unit. The carry flag C is
also affected by left shifts.
Repeat unit
The MAC includes a repeat unit allowing the repetition of some co-processor instructions up
to 2
times) or by the content of the Repeat Count (bits 12 to 0) in the MAC Repeat Word (MRW). If
the Repeat Count equals “N” the instruction will be executed “N+1” times. At each iteration of
a cumulative instruction the Repeat Count is tested for zero. If it is zero the instruction is
terminated else the Repeat Count is decremented and the instruction is repeated. During
such a repeat sequence, the Repeat Flag in MRW is set until the last execution of the
repeated instruction.
The syntax of repeated instructions is shown in the following examples:
In example 1, the instruction is repeated according to a 5-bit immediate value. The Repeat
Count in MRW is automatically loaded with this value minus one (MRW=23).
In this example, the instruction is repeated according to the Repeat Count in MRW. Notice that
due to the pipeline processing at least one instruction should be inserted between the write of
MRW and the next repeated instruction.
Repeat sequences may be interrupted. When an interrupt occurs during a repeat sequence,
the sequence is stopped and the interrupt routine is executed. The repeat sequence resumes
at the end of the interrupt routine. During the interrupt, MR remains set, indicating that a
repeated instruction has been interrupted and the Repeat Count holds the number (minus 1)
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1
1
1
No shift (Unmodified)
Up to 8-bit Arithmetic Left Shift
Up to 8-bit Arithmetic Right Shift
13
(8192) times. The repeat count may be specified either by an immediate value (up to 31
Repeat #24 times
CoMAC[IDX0+],[R0+]
MOV MRW, #00FFh
NOP
Repeat MRW times
CoMACM [IDX1-],[R2+]
; repeated 24 times
; load MRW
; instruction latency
; repeated 256 times