ST10F276Z5 STMicroelectronics, ST10F276Z5 Datasheet - Page 201

• Manufacturer Part Number: ST10F276Z5
• Description: 16-BIT MICROCONTROLLER WITH MAC UNIT, UP TO 832 KBYTES FLASH MEMORY AND UP TO 68 KBYTES RAM
• Manufacturer: STMicroelectronics

Specifications of ST10F276Z5

• Single Voltage Supply: 5V ±10% (embedded regulator for 1.8 V core supply)

ST10F276Z5
23.8.9
23.8.10
23.8.11
Example 2
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PLL Jitter
Two kinds of PLL jitter are defined:
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Jitter at the PLL output is caused by:
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Jitter in the input clock
PLL acts like a low pass filter for any jitter in the input clock. Input Clock jitter with the
frequencies within the PLL loop bandwidth is passed to the PLL output and higher frequency
jitter (frequency > PLL bandwidth) is attenuated at 20dB/decade.
Noise in the PLL loop
This condition again is attributed to the following sources:
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Device noise of the circuit in the PLL
Long term jitter is inversely proportional to the bandwidth of the PLL: The wider the loop
bandwidth, the lower the jitter due to noise in the loop. Moreover, long term jitter is
practically independent of the multiplication factor.
The most noise sensitive circuit in the PLL circuit is definitely the VCO (Voltage Controlled
Oscillator). There are two main sources of noise: Thermal (random noise, frequency
independent thus practically white noise) and flicker (low frequency noise, 1/f). For the
frequency characteristics of the VCO circuitry, the effect of the thermal noise results in a 1/f
region in the output noise spectrum, while the flicker noise in a 1/f
PLL input and supposing that the VCO is dominated by its 1/f
accumulated jitter is proportional to the square root of N, where N is the number of clock
F
P0(15:13) = ‘100’ (multiplication by 5)
PLL input frequency = 2 MHz
VCO frequency = 80 MHz
PLL output frequency = 40 MHz (VCO frequency divided by 2)
F
Self referred single period jitter
Also called "Period Jitter", it can be defined as the difference of the T
where T
minimum time period of the PLL output clock.
Self referred long term jitter
Also called "N period jitter", it can be defined as the difference of T
T
minimum time difference between N + 1 clock rising edges. Here N should be kept
sufficiently large to have the long term jitter. For N = 1, this becomes the single period
jitter.
Jitter in the input clock
Noise in the PLL loop
Device noise of the circuit in the PLL
Noise in supply and substrate
XTAL
CPU
max
is the maximum time difference between N + 1 clock rising edges and T
= 40 MHz (no effect of output prescaler)
= 8 MHz
max
is the maximum time period of the PLL output clock and T
2
noise, the R.M.S. value of the
Electrical characteristics
3
. Assuming a noiseless
max
max
min
and T
and T
is the
min
min
min
, where
201/239
is the
,
2