ST10F276Z5 STMicroelectronics, ST10F276Z5 Datasheet

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... Single voltage supply ±10% (embedded regulator for 1.8 V core supply) Max CPU Iflash Xflash frequency 64 MHz 512 Kbytes 320 Kbytes 40 MHz 512 Kbytes Rev 2 ST10F276Z5 7G_3D PQFP144 3.4mm LQFP144 1.4mm 2 C standard interface Temperature range RAM (°C) 68KB -40/+125 68KB ...

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... XFlash interface control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Protection registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Flash non volatile write protection X register low . . . . . . . . . . . . . . . . . . 38 Flash non volatile write protection X register high . . . . . . . . . . . . . . . . . 39 Flash non volatile write protection I register low . . . . . . . . . . . . . . . . . . 39 Flash non volatile write protection I register high . . . . . . . . . . . . . . . . . . 39 Flash non volatile access protection register ST10F276Z5 ...

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... ST10F276Z5 4.5.7 4.5.8 4.5.9 4.5.10 4.5.11 4.6 Write operation examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4.7 Write operation summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 5 Bootstrap loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 5.1 Selection among user-code, standard or alternate bootstrap . . . . . . . . . 47 5.2 Standard bootstrap loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 5.2.1 5.2.2 5.2.3 5.2.4 5.2.5 5.2.6 5.2.7 5.2.8 5.3 Standard bootstrap with UART (RS232 or K-Line 5.3.1 5.3.2 5.3.3 5.3.4 5.3.5 5.4 Standard bootstrap with CAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 5.4.1 5.4.2 5.4.3 5.4.4 5.4.5 5.4.6 5.4.7 5.5 Comparing the old and the new bootstrap loader . . . . . . . . . . . . . . . . . . 65 5.5.1 5.5.2 Flash non volatile access protection register 1 low . . . . . . . . . . . . . . . . 40 Flash non volatile access protection register 1 high ...

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... Parallel ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 12.2 I/Os special features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 4/239 Activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 ST10 configuration in alternate boot mode . . . . . . . . . . . . . . . . . . . . . . 67 Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Exiting alternate boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Alternate boot user software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 User/alternate mode signature integrity check . . . . . . . . . . . . . . . . . . . 68 Alternate boot user software aspects . . . . . . . . . . . . . . . . . . . . . . . . . . 68 EMUCON register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Internal decoding of test modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 ST10F276Z5 ...

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... ST10F276Z5 12.2.1 12.2.2 12.3 Alternate port functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 13 A/D converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 14 Serial channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 14.1 Asynchronous / synchronous serial interfaces . . . . . . . . . . . . . . . . . . . . . 96 14.2 ASCx in asynchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 14.3 ASCx in synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 14.4 High speed synchronous serial interfaces . . . . . . . . . . . . . . . . . . . . . . . . interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 16 CAN modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 16.1 Configuration support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 16.2 CAN bus configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 17 Real-time clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 18 Watchdog timer ...

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... A/D converter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 23.7.1 23.7.2 23.7.3 6/239 Protected Power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Interruptible Power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Entering Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Exiting Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Real-time clock and Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Power reduction modes summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Conversion timing control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 A/D conversion accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 Total unadjusted error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 ST10F276Z5 ...

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... ST10F276Z5 23.7.4 23.7.5 23.7.6 23.8 AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 23.8.1 23.8.2 23.8.3 23.8.4 23.8.5 23.8.6 23.8.7 23.8.8 23.8.9 23.8.10 Jitter in the input clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 23.8.11 Noise in the PLL loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 23.8.12 PLL lock/unlock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 23.8.13 Main oscillator specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 23.8.14 32 kHz Oscillator specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 23.8.15 External clock drive XTAL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 23.8.16 Memory cycle variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 23.8.17 External memory bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 23.8.18 Multiplexed bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 23 ...

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... Contents 25 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 26 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 8/239 ST10F276Z5 ...

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... Table 26. Flash non volatile access protection register 1 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 27. Summary of access protection level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 28. Flash write operations Table 29. ST10F276Z5 boot mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 30. ST10 configuration in BSL mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table 31. ST10 configuration in UART BSL mode (RS232 or K-line Table 32. ST10 configuration in CAN BSL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Table 33. ...

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... Data retention characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 Table 96. A/D Converter programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 Table 97. On-chip clock generator selections 198 Table 98. Internal PLL divider mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 Table 99. PLL lock/unlock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 Table 100. Main oscillator specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 Table 101. Negative resistance (absolute min. value @125oC / VDD = 4 204 10/239 ST10F276Z5 ...

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... ST10F276Z5 Table 102. 32 kHz Oscillator specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 Table 103. Minimum values of negative resistance (module 205 Table 104. External clock drive timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 Table 105. Memory cycle variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 Table 106. Multiplexed bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 Table 107. Demultiplexed bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 Table 108. CLKOUT and READY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 Table 109 ...

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... Figure 7. Hardware provisions to activate the BSL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Figure 8. Memory configuration after reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Figure 9. UART bootstrap loader sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Figure 10. Baud rate deviation between host and ST10F276Z5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Figure 11. CAN bootstrap loader sequence Figure 12. Bit rate measurement over a predefined zero-frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Figure 13. Reset boot sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Figure 14. ...

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... Input/output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 Figure 51. Float waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 Figure 52. Generation mechanisms for the CPU clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 Figure 53. ST10F276Z5 PLL jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 Figure 54. Crystal oscillator and resonator connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 Figure 55. 32 kHz crystal oscillator connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 Figure 56. External clock drive XTAL1 206 Figure 57 ...

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... Flash memory, on-chip high-speed RAM, and clock generation via PLL. The ST10F276Z5 is processed in 0.18 µm CMOS technology. The MCU core and the logic is supplied with 1.8 V on-chip voltage regulator. The part is supplied with a single 5 V supply and I/Os work ...

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... CMOS (with up to 800 mV of hysteresis). ● Output transition is not programmable. ● CAN module is enhanced: the ST10F276Z5 implements two C-CAN modules, so the programming model is slightly different. Besides, the possibility to map in parallel the two CAN modules is added (on P4.5/P4.6). ● ...

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... Logic symbol 16/239 XTAL1 XTAL2 XTAL3 XTAL4 RSTIN RSTOUT V AREF V ST10F276Z5 AGND NMI STBY READY ALE WRL Port 5 16-bit ST10F276Z5 Port 0 16-bit Port 1 16-bit Port 2 16-bit Port 3 15-bit Port 4 8-bit Port 6 8-bit Port 7 8-bit Port 8 8-bit RPD ...

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... P5.1 / AN1 P5.2 / AN2 P5.3 / AN3 P5.4 / AN4 P5.5 / AN5 P5.6 / AN6 P5.7 / AN7 P5.8 / AN8 P5.9 / AN9 ST10F276Z5 Pin data 108 P0H.0 / AD8 107 P0L.7 / AD7 106 P0L.6 / AD6 105 P0L.5 / AD5 104 P0L ...

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... CAPCOM2: CC20 capture input / compare output P8.5 CC21IO CAPCOM2: CC21 capture input / compare output P8.6 CC22IO CAPCOM2: CC22 capture input / compare output RxD1 ASC1: Data input (Asynchronous) or I/O (Synchronous) P8.7 CC23IO CAPCOM2: CC23 capture input / compare output TxD1 ASC1: Clock / Data output (Asynchronous/Synchronous) ST10F276Z5 Function ...

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... ST10F276Z5 Table 2. Pin description (continued) Symbol Pin Type 19-26 I P7.0 - P7.7 ... ... I/O ... ... 26 I/O 27-36 I 39- P5 P5.10 - P5. 47-54 I/O 57-64 47 I/O ... ... P2.0 - P2.7 54 I/O P2.8 - P2.15 57 I/O I ... ... 64 I 8-bit bidirectional I/O port, bit-wise programmable for input or output via direction bit. Programming an I/O pin as input forces the corresponding output driver to high impedance state. Port 7 outputs can be configured as push-pull or open drain drivers ...

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... ASC0: clock / data output (asynchronous/synchronous) P3.11 RxD0 ASC0: data input (asynchronous) or I/O (synchronous) P3.12 BHE External memory high byte enable signal WRH External memory high byte write strobe P3.13 SCLK0 SSC0: master clock output / slave clock input System clock output (programmable divider on CPU P3.15 CLKOUT clock) ST10F276Z5 Function ...

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... ST10F276Z5 Table 2. Pin description (continued) Symbol Pin Type 85-92 I P4.0 –P4 WR/WRL 96 O READY READY ALE 98 O Port 8-bit bidirectional I/O port bit-wise programmable for input or output via direction bit. Programming an I/O pin as input forces the corresponding output driver to high impedance state ...

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... I 22/239 External access enable pin. A low level applied to this pin during and after Reset forces the ST10F276Z5 to start the program from the external memory space. A high level forces the ST10F276Z5 to start in the internal memory space. This pin is also used (when Standby mode is entered, that is the device under reset and main V ...

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... ST10F276Z5 Table 2. Pin description (continued) Symbol Pin Type XTAL1 138 I XTAL2 137 O XTAL3 143 I XTAL4 144 O RSTIN 140 I RSTOUT 141 O NMI 142 AREF AGND RPD 84 - 17, 46, 72,82,93 109, 126, 136 18,45, 55,71, V 83,94 110, 127, 139 XTAL1 Main oscillator amplifier circuit and/or external clock input. ...

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... Functional description 3 Functional description The ST10F276Z5 architecture combines advantages of both RISC and CISC processors and an advanced peripheral subsystem. The block diagram gives an overview of the different on-chip components and the high bandwidth internal bus structure of the ST10F276Z5. Figure 3. Block diagram XFLASH 320K ...

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... ST10F276Z5 4 Internal Flash memory 4.1 Overview The on-chip Flash is composed by two matrix modules each one containing one array divided in two banks that can be read and modified independently one of the other: one bank can be read while another bank is under modification. Figure 4. Flash modules structure ...

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... FFFF 0x0007 0000 - 0x0007 FFFF 0x0008 0000 - 0x0008 FFFF 0x0009 0000 - 0x0009 FFFF 0x000A 0000 - 0x000A FFFF 0x000B 0000 - 0x000B FFFF 0x000C 0000 - 0x000C FFFF 0x000D 0000 - 0x000D FFFF ST10F276Z5 (Table 3): note that with this Addresses Size ...

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... ST10F276Z5 Table 5. Flash modules sectorization (write operations or with roms1=’1’) Bank Bank 0 Test-Flash (B0TF) Bank 0 Flash 0 (B0F0) Bank 0 Flash 1 (B0F1) Bank 0 Flash 2 (B0F2) Bank 0 Flash 3 (B0F3) B0 Bank 0 Flash 4 (B0F4) Bank 0 Flash 5 (B0F5) Bank 0 Flash 6 (B0F6) Bank 0 Flash 7 (B0F7) Bank 0 Flash 8 (B0F8) ...

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... DFB0 - 0x000E DFB3 0x000E DFB4 - 0x000E DFB7 0x000E DFB8 - 0x000E DFB9 0x000E DFBC - 0x000E DFBF 0x000E E000 - 0x000E E001 ST10F276Z5 Addresses Size bus size 8 byte 8 byte 4 byte 2 byte ...

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... ST10F276Z5 Bank, or from the other module or again from another memory (internal RAM or external memory). Note: During a Write operation, when bit LOCK of FCR0 is set forbidden to write into the Flash Control Registers. 4.3.1 Power supply drop If during a write operation the internal low voltage supply drops below a certain internal voltage threshold, any write operation running is suddenly interrupted and the modules are reset to Read mode ...

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... SEQER of FER if the address written in FARH/L is not in the range 0x0EDFB0- 0x0EDFBF. SPR bit is automatically reset at the end of the Set Protection operation. 30/239 Function FCR Reserved SPR SMOD Function ST10F276Z5 Reset value: 0000h Reserved 0 ...

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... ST10F276Z5 Table 8. Flash control register 0 high (continued) Bit Sector erase This bit must be set to select the Sector Erase operation in the Flash modules. The Sector Erase operation allows to erase all the Flash locations to 0xFF. From 1 to all the SER sectors of the same Bank (excluded Test-Flash for Bank B0) can be selected to be erased through bits BxFy of FCR1H/L registers before starting the execution by setting bit WMS ...

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... FCR Reserved FCR B0F9 B0F8 B0F7 B0F6 B0F5 B0F4 B0F3 B0F2 B0F1 B0F0 Function Table ST10F276Z5 Reset value: 0000h B2F2 B2F1 B2F0 RS RS Reset value: 0000h ...

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... ST10F276Z5 4.4.4 Flash control register 1 high The Flash control register 1 high (FCR1H), together with Flash control register 1 low (FCR1L), is used to select the sectors to erase, or during any write operation to monitor the status of each sector and each bank of the module selected by SMOD bit of FCR0H. First diagram shows FCR1H meaning when SMOD=0 ...

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... Function FCR Function ST10F276Z5 BxFy = 1 meaning Erase error in sector y of bank x Erase suspended in sector y of bank x Don’t care Reset value: FFFFh DIN6 DIN5 DIN4 DIN3 DIN2 DIN1 ...

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... ST10F276Z5 4.4.7 Flash data register 1 low FDR1L (0x0E 000C DIN15 DIN14 DIN13 DIN12 DIN11 DIN10 Table 14. Flash data register 1 low Bit Data Input 15:0 DIN(15:0) These bits must be written with the Data to program the Flash with the following operations: Word Program (32-bit), Double Word Program (64-bit) and Set Protection. ...

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... FCR reserved WPF RESER SEQER RC Reset value: 0000h ADD20 ADD19 ADD18 ADD17 ADD16 Function Reset value: 0000h reserved 10ER PGER ERER Function ST10F276Z5 ERR RC RC ...

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... These three bits are the binary coding of the number of wait states introduced by the XFLASH interface through the XBUS internal READY signal. Default value after reset is 1111, that is the wait states are set. The following recommendations for the WS(3:0) ST10F276Z5 are hereafter reported: For f For f XBUS ...

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... Since these Non Volatile cells are dedicated to Protection registers, once W2PPR bit is set, the configuration of protection setting is frozen, and can only be modified executing a Temporary Write Unprotection operation. 38/239 NVR reserved Function ST10F276Z5 Delivery value: FFFFh W2P2W2P1W2P0 ...

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... ST10F276Z5 4.5.3 Flash non volatile write protection X register high FNVWPXRH (0x0E DF B2 Table 21. Flash non volatile write protection X register high Bit Write Protection Bank 3 / Sectors 1-0 (XFLASH) W3P(1:0) These bits, if programmed at 0, disable any write access to the sectors of Bank 3 (XFLASH). 4.5.4 Flash non volatile write protection I register low ...

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... Bit PDSx can be programmed at 0 only if bit PENx-1 has already been programmed at 0. 40/239 NVR reserved Function NVR Function ST10F276Z5 Delivery value: ACFFh DBGP RW Delivery value: FFFFh ACCP RW ...

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... ST10F276Z5 4.5.8 Flash non volatile access protection register 1 high FNVAPR1H (0x0E DFBE PEN15 PEN14 PEN13 PEN12 PEN11 PEN10 PEN9 PEN8 PEN7 PEN6 PEN5 PEN4 PEN3 PEN2 PEN1 PEN0 Table 26. Flash non volatile access protection register 1 high Bit Protections Enable 15-0 If bit PENx is programmed at 0 and bit PDSx+1 is erased at 1, the action of bit ACCP PEN15-0 is enabled again ...

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... RAM area not possible to deduce it by reading the non volatile register content (a temporary unprotection cannot be detected). 42/239 Read IFLASH / Read XFLASH Jump to /Jump to IFLASH XFLASH No / Yes Yes / Yes No / Yes Yes / Yes ST10F276Z5 Read FLASH Write FLASH Registers Registers Yes No Yes No ...

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... ST10F276Z5 4.6 Write operation examples In the following, examples for each kind of Flash write operation are presented. Word program Example: 32-bit Word Program of data 0xAAAAAAAA at address 0x0C5554 in XFLASH Module. FCR0H|= 0x2000; /*Set WPG in FCR0H*/ FARL = 0x5554; /*Load Add in FARL*/ FARH = 0x000C; /*Load Add in FARH*/ FDR0L = 0xAAAA ...

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... FARH = 0x000E;/*Load Add of register FNVWPIRL in FARH*/ FDR0L = 0xFFF0;/*Load Data in FDR0L*/ FDR0H = 0xFFFF;/*Load Data in FDR0H*/ FCR0H|= 0x8000;/*Operation start*/ Notice that bit SMOD of FCR0H must not be set, since Write Protection bits of IFLASH Module are stored in Test-Flash (XFLASH Module). 44/239 ST10F276Z5 ...

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... ST10F276Z5 Example 2: Enable Access and Debug Protection. FCR0H|= 0x0100;/*Set SPR in FCR0H*/ FARL = 0xDFB8;/*Load Add of register FNVAPR0 in FARL*/ FARH = 0x000E;/*Load Add of register FNVAPR0 in FARH*/ FDR0L = 0xFFFC;/*Load Data in FDR0L*/ FCR0H|= 0x8000;/*Operation start*/ Example 3: Disable in a permanent way Access and Debug Protection. ...

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... Operation Word Program (32-bit) Double Word Program (64-bit) Sector Erase Set Protection Program/Erase Suspend 46/239 Select bit Address and Data FARL/FARH WPG FDR0L/FDR0H FARL/FARH DWPG FDR0L/FDR0H FDR1L/FDR1H SER FCR1L/FCR1H SPR FDR0L/FDR0H SUSP None ST10F276Z5 Start bit WMS WMS WMS WMS None ...

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... ST10F276Z5 5 Bootstrap loader The ST10F276Z5 features innovative boot capabilities in order to support: ● User defined bootstrap (see Alternate bootstrap loader) ● Bootstrap via UART or bootstrap via CAN for the standard bootstrap 5.1 Selection among user-code, standard or alternate bootstrap The selection among user-code, standard bootstrap or alternate bootstrap is made by special combinations on Port0L[5 ...

Page 48

... Entering the standard bootstrap loader As with the old ST10 bootstrap mode, the ST10F276Z5 enters BSL mode if pin P0L.4 is sampled low at the end of a hardware reset. In this case, the built-in bootstrap loader is activated independently of the selected bus mode. The bootstrap loader code is stored in a special Test-Flash ...

Page 49

... ST10F276Z5 Valid dominant bit on CAN1 RxD The ST10F276Z5 starts bootstrapping via CAN1; the bootstrapping method is new and is described in the next paragraph 5.4. loader. It clearly illustrates how the new functionalities are implemented: ● UART: UART has priority over CAN after a falling edge on CAN1_RxD until the first valid rising edge on CAN1_RxD ...

Page 50

... Other than after a normal reset the watchdog timer is disabled, so the bootstrap loading sequence is not time limited. Depending on the selected serial link (UART0 or CAN1), pin TxD0 or CAN1_TxD is configured as output, so the ST10F276Z5 can return the acknowledge byte. Even if the internal IFLASH is enabled, a code cannot be executed from it ...

Page 51

... P0L.4 low. After loading a preselected number of bytes, the ST10F276Z5 begins executing the downloaded program. 3. The first level user code runs on the ST10F276Z5. Typically, this first level user code is another loader that downloads the application software into the device. 4. ...

Page 52

... In default configuration, to program address 0, the user must put the value 01'0000h in the FARL and FARH registers but to verify the content of the address 0 a read to 00'0000h must be performed. 52/239 P0L.4 R P0L.4 8kΩ max. Circuit 1 ST10F276Z5 External signal Normal boot BSL R P0L.4 8kΩ max. Circuit 2 ...

Page 53

... ST10F276Z5 Figure 8. Memory configuration after reset BSL mode active EA pin Code fetch from internal FLASH area Data fetch from internal FLASH area 1. As long as the device is in BSL, the user’s software should not try to execute code from the internal IFlash, as the fetches are redirected to the Test-Flash ...

Page 54

... Same bootstrapping steps; ● Same bootstrap method: Analyze the timing of a predefined byte, send back an acknowledge byte, load a fixed number of bytes and run; ● Same functionalities: Boot with different crystals and PLL ratios. 54/239 ST10F276Z5 terminated. The device Figure 6 - Step ...

Page 55

... CPU clock, initializes the serial interface ASC0 accordingly and switches pin TxD0 to output. Using this baud rate, an acknowledge byte is returned to the host that provides the loaded data. The acknowledge byte is D5h for the ST10F276Z5 ...

Page 56

... BTYP field, bit 7 and 6, is set according to Port0 configuration. Other than after a normal reset, the watchdog timer is disabled, so the bootstrap loading sequence is not time limited. Pin TxD0 is configured as output, so the ST10F276Z5 can return the acknowledge byte. Even if the internal IFLASH is enabled, a code cannot be executed from it ...

Page 57

... This baud rate deviation is a nonlinear function depending on the CPU clock and the baud rate of the host. The maxima of the function (F the smaller baud rate prescaler factors and the implied higher quantization error (see Figure 10). Figure 10. Baud rate deviation between host and ST10F276Z5 F B 2.5% B ...

Page 58

... BSL initialization time, > 1ms @ fCPU = 40 MHz. 2. Zero frame (CAN message: standard DLC = 0), sent by host. 3. CAN message (standard ID = E6h, DLC = 3, Data0 = D5h, Data1-Data2 = IDCHIP_low-high), sent by the ST10F276Z5 on request. 4. 128 bytes of code / data, sent by host. 5. Caution: CAN1_TxD is only driven a certain time after reception of the zero byte (1.3ms @ fCPU = 40 MHz). ...

Page 59

... Entering the CAN bootstrap loader The ST10F276Z5 enters BSL mode if pin P0L.4 is sampled low at the end of a hardware reset. In this case, the built-in bootstrap loader is activated independently of the selected bus mode. The bootstrap loader code is stored in a special Test-Flash; no part of the standard mask ROM or Flash memory area is required for this ...

Page 60

... BTYP field, bit 7 and 6, is set according to Port0 configuration. Other than after a normal reset, the watchdog timer is disabled, so the bootstrap loading sequence is not time limited. Pin CAN1_TxD1 is configured as output, so the ST10F276Z5 can return the identification frame. Even if the internal IFLASH is enabled, a code cannot be executed from it ...

Page 61

... This process may go through several iterations or may directly execute the final application. In all cases the ST10F276Z5 still runs in BSL mode, that is, with the watchdog timer disabled and limited access to the internal Flash area. All code fetches from the internal Flash area (01’ ...

Page 62

... CPU clk cycle) ; Test if 5th stuff bit detected ; Stop timer ; here the 5th stuff bit is detected: ; PT0 = 29 Bit_Time (25D and 4R) th recessive bit is: PT0 = 58 x (BRP + Tseg1 + Tseg2) 8 ≤ Tseg1 + Tseg2 ≤ 25 464 BRP) ≤ PT0 ≤ 1450 BRP) ST10F276Z5 ...

Page 63

... ST10F276Z5 Table 33. BRP and PT0 values BRP The error coming from the measurement of the 29 bit is maximal for the smallest BRP value and the smallest number of ticks in PT0. Therefore: To improve precision, the aim is to have the smallest BRP so that the time quantum is the smallest possible ...

Page 64

... The content of the bit timing register is: 0x1640. This gives a sample point at 80%. Note: The (Re)Synchronization Jump Width is fixed to 2 time quanta. 5.4.7 Bootstrap via CAN After the bootstrap phase, the ST10F276Z5 CAN module is configured as follows: ● The pin P4.6 is configured as output (the latch value is ‘1’ = recessive) to assume CAN1_TxD function. ● ...

Page 65

... ST10F276Z5 5.5 Comparing the old and the new bootstrap loader The following tables summarizes the differences between the old ST10 (boot via UART only) bootstrap and the new one (boot via UART or CAN). Table 34. Software topics summary Old bootstrap loader Uses only 32 bytes in Dual- Port RAM from 00’ ...

Page 66

... Alternate boot is activated with the combination ‘01’ on Port0L[5..4] at the rising edge of RSTIN. 5.6.2 Memory mapping The ST10F276Z5 has the same memory mapping for standard boot mode and for alternate boot mode: ● Test-Flash: Mapped from 00’0000h. The Standard Bootstrap Loader can be started by executing a jump to the address of this routine (JMPS 00’ ...

Page 67

... ST10F276Z5 5.6.4 ST10 configuration in alternate boot mode When the ST10F276Z5 enters BSL mode via CAN, the configuration shown in automatically set (values that deviate from the normal reset values are marked in bold). Table 36. ST10 configuration in alternate boot mode Function or register Watchdog timer Register SYSCON ...

Page 68

... Alternate boot user software aspects User defined alternate boot code must start at 09’0000h. A new SFR created on the ST10F276Z5 indicates that the device is running in Alternate Boot mode: Bit 5 of EMUCON (mapped at 0xFE0Ah) is set when the alternate boot is selected by the reset configuration. ...

Page 69

... Alternate Boot mode is selected by reset configuration on P0L[5..4]: This bit is set if P0L[5..4] = ‘01’ during hardware reset. 5.6.11 Internal decoding of test modes The test mode decoding logic is located inside the ST10F276Z5 Bus Controller. The decoding is as follows: ● Alternate Boot mode decoding: (P0L.5 & P0L.4) ● ...

Page 70

... Selective Bootstrap Loader to poll only RxD0 (no boot via CAN). ● 0xXX02 configures the Selective Bootstrap Loader to poll only CAN1_RxD (no boot via UART). ● Other values allow the ST10F276Z5 to execute an endless loop into the Test-Flash. 70/239 ST10F276Z5 Function ...

Page 71

... ST10F276Z5 Figure 13. Reset boot sequence Software checks user reset vector (K1 is OK?) Software Checks alternate reset vector (K2 is OK?) Long jump to ABM / User Flash Start at 09’0000h RSTIN Yes (P0L[5..4] = ‘01’) Boot mode? Yes (P0L[5..4] = ‘10’ not not Read 00’ ...

Page 72

... SFRs. Additional hardware has been added for a separate multiply and divide unit, a bit-mask generator and a barrel shifter. Most of the ST10F276Z5 instructions can be executed in one instruction cycle which requires 31.25ns at 64 MHz CPU clock. For example, shift and rotate instructions are processed in one instruction cycle independent of the number of bits to be shifted ...

Page 73

... ST10F276Z5 6.1 Multiplier-accumulator unit (MAC) The MAC coprocessor is a specialized coprocessor added to the ST10 CPU Core in order to improve the performances of the ST10 Family in signal processing algorithms. The standard ST10 CPU has been modified to include new addressing capabilities which enable the CPU to supply the new coprocessor with operands per instruction cycle. ...

Page 74

... Central processing unit (CPU) 6.2 Instruction set summary The Table 39 lists the instructions of the ST10F276Z5. The detailed description of each instruction can be found in the “ST10 Family Programming Manual”. Table 39. Standard instruction set summary Mnemonic ADD(B) ADDC(B) SUB(B) SUBC(B) MUL(U) DIV(U) DIVL(U) CPL(B) ...

Page 75

... ST10F276Z5 Table 39. Standard instruction set summary (continued) Mnemonic J(N)B JBC JNBS CALLA, CALLI, CALLR CALLS PCALL TRAP PUSH, POP SCXT RET RETS RETP RETI SRST IDLE PWRDN SRVWDT DISWDT EINIT ATOMIC EXTR EXTP(R) EXTS(R) NOP Description Jump relative if direct bit is (not) set ...

Page 76

... Central processing unit (CPU) 6.3 MAC coprocessor specific instructions The Table 40 lists the MAC instructions of the ST10F276Z5. The detailed description of each instruction can be found in the “ST10 Family Programming Manual”. Note that all MAC instructions are encoded on 4 bytes. Table 40. MAC instruction set summary ...

Page 77

... ST10F276Z5 7 External bus controller All of the external memory accesses are performed by the on-chip external bus controller. The EBC can be programmed to single chip mode when no external memory is required one of four different external memory access modes: ● 16- / 18- / 20- / 24-bit addresses and 16-bit data, demultiplexed ● ...

Page 78

... When this counter reaches zero, a standard interrupt is performed to the corresponding source related vector location. PEC services are very well suited to perform the transmission or the reception of blocks of data. The ST10F276Z5 has 8 PEC channels, each of them offers such fast interrupt-driven data transfer capabilities. ...

Page 79

... ST10F276Z5 Table 41. Interrupt sources (continued) Source of Interrupt or PEC Service Request CAPCOM Register 6 CAPCOM Register 7 CAPCOM Register 8 CAPCOM Register 9 CAPCOM Register 10 CAPCOM Register 11 CAPCOM Register 12 CAPCOM Register 13 CAPCOM Register 14 CAPCOM Register 15 CAPCOM Register 16 CAPCOM Register 17 CAPCOM Register 18 CAPCOM Register 19 CAPCOM Register 20 CAPCOM Register 21 ...

Page 80

... XP2IE XP2INT XP3IR XP3IE XP3INT 2 C, PWM1 and RTC need some resources to implement interrupt Figure 16, the principle is explained through a simple XIRxSEL[15:8] Interrupt Enable bits XIRxSEL[7:0] Interrupt Flag bits ST10F276Z5 Vector Trap Location Number 00’0098h 26h 00’009Ch 27h 00’00A0h 28h 00’00A4h 29h 00’ ...

Page 81

... ST10F276Z5 available vector. If more than one source is enabled to issue the request, the service routine will have to take care to identify the real event to be serviced. This can easily be done by checking the flag bits (Byte Low of XIRxSEL register). Note that the flag bits can also ...

Page 82

... RESET (2) : NMI NMITRAP STKOF STOTRAP STKUF STUTRAP (3) : UNDOPC BTRAP MACTRP BTRAP PRTFLT BTRAP ILLOPA BTRAP ILLINA BTRAP ILLBUS BTRAP ST10F276Z5 XP1INT XP2INT XP3INT x Vector Trap Location Number 00’0000h 00h 00’0000h 00h 00’0000h 00h 00’0008h 02h 00’0010h 04h 00’0018h 06h 00’0028h 0Ah 00’ ...

Page 83

... ST10F276Z5 9 Capture / compare (CAPCOM) units The ST10F276Z5 has two 16-channel CAPCOM units which support generation and control of timing sequences channels with a maximum resolution of 125 MHz CPU clock. The CAPCOM units are typically used to handle high speed I/O tasks such as pulse and waveform generation, pulse width modulation (PMW), Digital to Analog (D/A) conversion, software timing, or time recording relative to external events ...

Page 84

... ST10F276Z5 111b 1024 39.1 kHz 25.6 µs 1.678 s 111b 1024 64 kHz 16.0 µs 1.049 s ...

Page 85

... ST10F276Z5 10 General purpose timer unit The GPT unit is a flexible multifunctional timer/counter structure which is used for time related tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation, or pulse multiplication. The GPT unit contains five 16-bit timers organized into two separate modules GPT1 and GPT2 ...

Page 86

... Mode Control 2n n=3...10 100b 101b 110b 128 256 512 500 kHz 250 kHz 128 kHz 2.0 µs 4.0 µs 8.0 µs 131.1 ms 262.1 ms 524.3 ms U/D Interrupt GPT1 Timer T2 Request T3OUT T3OTL GPT1 Timer T3 U/D Interrupt Request Interrupt GPT1 Timer T4 Request U/D ST10F276Z5 111b 1024 64 kHz 16.0 µs 1.049 s ...

Page 87

... ST10F276Z5 10.2 GPT2 The GPT2 module provides precise event control and time measurement. It includes two timers (T5, T6) and a capture/reload register (CAPREL). Both timers can be clocked with an input clock which is derived from the CPU clock via a programmable prescaler or with external signals. The count direction (up/down) for each timer is programmable by software or may additionally be altered dynamically by an external signal on a port pin (TxEUD) ...

Page 88

... Figure 18. Block diagram of GPT2 T5EUD CPU Clock T5IN CAPIN T6IN CPU Clock T6EUD 88/239 T5 2n n=2...9 GPT2 Timer T5 Mode Control Clear Capture GPT2 CAPREL T6 GPT2 Timer T6 Mode 2n n=2...9 Control ST10F276Z5 U/D Interrupt Request Interrupt Request Reload Interrupt Request Toggle FF T60TL T6OUT U/D to CAPCOM Timers ...

Page 89

... ST10F276Z5 11 PWM modules Two pulse width modulation modules are available on ST10F276Z5: standard PWM0 and XBUS PWM1. They can generate up to four PWM output signals each, using edge-aligned or centre-aligned PWM. In addition, the PWM modules can generate PWM burst signals and single shot outputs. The resolutions ...

Page 90

... Mode Resolution Mode 0 CPU Clock/1 15.6 ns CPU Clock/64 Mode 1 CPU Clock/1 15.6 ns CPU Clock/64 90/239 8-bit 10-bit 250 kHz 62.5 kHz 1.0µs 3.91 kHz 976.6 Hz 125 kHz 31.25 kHz 1.0µs 1.95 kHz 488.28 Hz ST10F276Z5 12-bit 14-bit 16-bit 15.63 kHz 3.91Hz 977 Hz 244.1 Hz 61.01 Hz 15.26 Hz 7.81 kHz 1.95 kHz 488.3 Hz 122.07 Hz 30.52 Hz 7.63 Hz ...

Page 91

... Parallel ports 12.1 Introduction The ST10F276Z5 MCU provides up to 111 I/O lines with programmable features. These capabilities bring very flexible adaptation of this MCU to wide range of applications. The ST10F276Z5 has nine groups of I/O lines gathered as follows: ● Port two time 8-bit port named P0L (Low as less significant byte) and P0H (high as most significant byte) ● ...

Page 92

... I/Os special features 12.2.1 Open drain mode Some of the I/O ports of ST10F276Z5 support the open drain capability. This programmable feature may be used with an external pull-up resistor, in order to get an AND wired logical function. This feature is implemented for ports P2, P3, P4, P6, P7 and P8 (see respective sections), and is controlled through the respective Open Drain Control Registers ODPx. ...

Page 93

... ST10F276Z5 ‘1’, because its output is ANDed with the alternate output data (except for PWM output signals). If the alternate input function of a pin is used, the direction of the pin must be programmed for input (DPx.y=‘0’ external device is driving the pin. The input direction is the default after reset ...

Page 94

... The ST10F276Z5 has 16+8 multiplexed input channels on Port 5 and Port 1. The selection between Port 5 and Port 1 is made via a bit in a XBus register. Refer to the User Manual for a detailed description. ...

Page 95

... ST10F276Z5 register. The data can be transferred to the RAM by interrupt software management or using the PEC data transfer. ● Wait for ADDAT read mode: When using continuous modes, in order to avoid to overwrite the result of the current conversion by the next one, the ADWR bit of ADCON control register must be activated ...

Page 96

... SSC1 (XBUS mapped). 14.1 Asynchronous / synchronous serial interfaces The asynchronous / synchronous serial interfaces (ASC0 and ASC1) provides serial communication between the ST10F276Z5 and other microcontrollers, microprocessors or external peripherals. 14.2 ASCx in asynchronous mode In asynchronous mode 9-bit data transfer, parity generation and the number of stop bits can be selected ...

Page 97

... The deviation errors given in the errors use a Baud rate crystal (providing a multiple of the ASC0 sampling frequency). 14.3 ASCx in synchronous mode In synchronous mode, data is transmitted or received synchronously to a shift clock which is generated by the ST10F276Z5. Half-duplex communication Baud (at 40 MHz possible in this mode. CPU Table 55. ...

Page 98

... High speed synchronous serial interfaces The High-Speed Synchronous Serial Interfaces (SSC0 and SSC1) provides flexible high- speed serial communication between the ST10F276Z5 and other microcontrollers, microprocessors or external peripherals. The SSCx supports full-duplex and half-duplex synchronous communication. The serial clock signal can be generated by the SSCx itself (master mode received from an external master (slave mode) ...

Page 99

... ST10F276Z5 Table 57. Synchronous baud rate and reload values (f Baud rate Reserved Can be used only with f lower) 6.6M Baud 5M Baud 2.5M Baud 1M Baud 100K Baud 10K Baud 1K Baud 306 Baud Table 58. Synchronous baud rate and reload values (f Baud rate Reserved Can be used only with f ...

Page 100

... C cell is disabled (clearing bit XI2CEN), P4.4 and P4.7 pins are standard I/ O controlled by P4, DP4 and ODP4. The speed of the I 2 Fast I C mode (100 to 400 kHz). 100/239 2 C Bus specification. The bus modes are supported interface may be selected between Standard mode (0 to 100 kHz) and ST10F276Z5 2 C Module can ...

Page 101

... ST10F276Z5 16 CAN modules The two integrated CAN modules (CAN1 and CAN2) are identical and handle the completely autonomous transmission and reception of CAN frames according to the CAN specification V2.0 part B (active based on the C-CAN specification. Each on-chip CAN module can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers ...

Page 102

... CAN bus configurations Depending on application, CAN bus configuration may be one single bus with a single or multiple interfaces or a multiple bus with a single or multiple interfaces. The ST10F276Z5 is able to support these two cases. Single CAN bus The single CAN Bus multiple interfaces configuration may be implemented using two CAN transceivers as shown in Figure 20 ...

Page 103

... ST10F276Z5 Multiple CAN bus The ST10F276Z5 provides two CAN interfaces to support such kind of bus configuration as shown in Figure 22. Figure 22. Connection to two different CAN buses (e.g. for gateway application) CAN_H CAN_L Parallel mode In addition to previous configurations, a parallel mode is supported. This is shown in Figure 23. Figure 23. Connection to one CAN bus with internal Parallel mode enabled 1 ...

Page 104

... Vice versa, when at power on and after Reset, the 32 kHz is not present, the main STBY oscillator drives the RTC counter, and since it is powered by the main power supply, it cannot be maintained running in Standby mode, while in Power-down mode the main oscillator is maintained running to provide the reference to the RTC module (if not disabled). 104/239 ST10F276Z5 ...

Page 105

... ST10F276Z5 18 Watchdog timer The Watchdog Timer is a fail-safe mechanism which prevents the microcontroller from malfunctioning for long periods of time. The Watchdog Timer is always enabled after a reset of the chip and can only be disabled in the time interval until the EINIT (end of initialization) instruction has been executed. ...

Page 106

... Status PONR Low Low LHWR High SHWR High WDTR (3) SWR for more details on minimum reset pulse duration. and Section 19.6). ST10F276Z5 Table Conditions Power-on (2) t > (1032 + 12) TCL + max(4 TCL, RSTIN 500 ns) t > max(4 TCL, 500 ns) RSTIN ≤ (1032 + 12) TCL + max(4 TCL, t RSTIN ...

Page 107

... ST10F276Z5 19.2 Asynchronous reset An asynchronous reset is triggered when RSTIN pin is pulled low while RPD pin is at low level. Then the device is immediately (after the input filter delay) forced in reset default state. It pulls low RSTOUT pin, it cancels pending internal hold states if any, it aborts all internal/external bus cycles, it switches buses (data, address and control signals) and I/O pin drivers to high-impedance, it pulls high Port0 pins ...

Page 108

... V drivers are sized to drive 18 currents of several tens of Ampere, so the current shall be limited by the external hardware. The limit of current is imposed by power dissipation considerations (Refer to Electrical Characteristics Section). and Figure 25 Asynchronous Power-on timing diagrams are reported, ST10F276Z5 pin should 18 ...

Page 109

... ST10F276Z5 Figure 24. Asynchronous power-on RESET ( XTAL1 RPD RSTIN RSTF (After Filter) P0[15:13] P0[12:2] P0[1:0] IBUS-CS (Internal) FLARST RST ≤ 1.2 ms (for resonator oscillation + PLL stabilization) ≤ 10.2 ms (for crystal oscillation + PLL stabilization) ≥ (for on-chip VREG stabilization) ≤ 2 TCL ... ≥ ≤ 500 ns 3 ...

Page 110

... PLL stabilization) ≥ 10.2 ms (for crystal oscillation + PLL stabilization) ≥ (for on-chip VREG stabilization) 1) 3..8 TCL ... ≥ ≤ 500 ns 3..4 TCL transparent transparent not transparent Latching point of Port0 for system start-up configuration Figure ST10F276Z5 not t. not t. not t. 8 TCL 37, Figure 38 ...

Page 111

... ST10F276Z5 Figure 26. Asynchronous hardware RESET ( RPD RSTIN RSTF (After Filter) P0[15:13] P0[12:2] P0[1:0] IBUS-CS (internal) FLARST RST This timing can be longer than Port0 settling time + PLL synchronization (if needed, that is 1. P0(15:13) changed). It can be longer than 500 ns to take into account of Input Filter on (1) ≥ ≤ ...

Page 112

... Timing of asynchronous Hardware Reset sequence are summarized in Figure 26 and Figure 112/239 1) ≥ ≤ 500 ns not transparent transparent not transparent transparent not transparent 27. ST10F276Z5 2) 3..8 TCL ≥ ≤ 500 ns 3..4 TCL not t. not t. not t. 8 TCL Latching point of Port0 for system start-up configuration pin. RSTIN ...

Page 113

... ST10F276Z5 19.3 Synchronous reset (warm reset) A synchronous reset is triggered when RSTIN pin is pulled low while RPD pin is at high level. In order to properly activate the internal reset logic of the device, the RSTIN pin must be held low, at least, during 4 TCL (2 periods of CPU clock): refer also to details on minimum reset pulse duration ...

Page 114

... For a Software or Watchdog reset events, an active synchronous reset is completed regardless of the RPD status important to highlight that the signal that makes RPD status transparent under reset is the internal RSTF (after the noise filter). 114/239 Figure 30 and Figure 31 Figure 26. There is no effect if RPD comes again above ST10F276Z5 reports the timing of ...

Page 115

... ST10F276Z5 Figure 28. Synchronous short / long hardware RESET ( ≤4 TCL RSTIN ≥ ≤ 500 ns RSTF (After Filter) P0[15:13] P0[12:2] P0[1:0] IBUS-CS (Internal) FLARST RST RSTOUT RPD 1. RSTIN assertion can be released there. Refer also to Section 21.1 for details on minimum pulse duration during the reset condition ( the asynchronous reset is then immediately entered ...

Page 116

... TCL 200 mA Discharge 19.6). ST10F276Z5 ≥ ≤ 500 ns not t. not t. 3..8 TCL3) 8 TCL 8 TCL At this time RSTF is sampled HIGH or LOW SHORT or LONG reset 2) VRPD > 2.5 V Asynchronous Reset not entered ...

Page 117

... ST10F276Z5 Figure 30. Synchronous long hardware RESET ( RSTIN RSTF (After Filter) P0[15:13] P0[12:2] P0[1:0] IBUS-CS (Internal) FLARST RST RSTOUT RPD 1. If during the reset condition (RSTIN low), RPD voltage drops below the threshold voltage (around 2.5 V for 5 V operation), the asynchronous reset is then immediately entered. ...

Page 118

... TCL At this time RSTF is sampled LOW LONG reset µ 200 A Discharge ). Section 19.6 ST10F276Z5 3..4 TCL not t. not t. not t. 3) 3..8 TCL 8 TCL 1) V > 2.5 V Asynchronous Reset not entered RPD ...

Page 119

... ST10F276Z5 19.4 Software reset A software reset sequence can be triggered at any time by the protected SRST (software reset) instruction. This instruction can be deliberately executed within a program, e.g. to leave bootstrap loader mode hardware trap that reveals system failure. On execution of the SRST instruction, the internal reset sequence is started. The microcontroller behavior is the same as for a synchronous short reset, except that only bits P0 ...

Page 120

... Figure 33 WDT unidirectional RESET ( RSTIN P0[15:13] P0[12:8] P0[7:2] P0[1:0] ALE RST RSTOUT 120/239 ≤ 2 TCL not transparent transparent not transparent not transparent ≤ 1024 TCL not transparent transparent not transparent not transparent 1024 TCL ST10F276Z5 not t. not t. 7 TCL not t. not t. 8 TCL ...

Page 121

... ST10F276Z5 19.6 Bidirectional reset As shown in the previous sections, the RSTOUT pin is driven active (low level) at the beginning of any reset sequence (synchronous/asynchronous hardware, software and watchdog timer resets). RSTOUT pin stays active low beyond the end of the initialization routine, until the protected EINIT instruction (End of Initialization) is completed. ...

Page 122

... RSTOUT 122/239 and Figure 36 summarize the timing for Software and Watchdog Figure 36 ≥ ≥ ≤ 500 ns ≤ 500 ns not transparent transparent not transparent not transparent ≤ 1024 TCL ST10F276Z5 shows the degeneration into not t. not t. ≤ 2 TCL 7 TCL ...

Page 123

... ST10F276Z5 Figure 35 WDT bidirectional RESET ( RSTIN ≥ ≤ 500 ns RSTF (After Filter) P0[15:13] P0[12:8] P0[7:2] P0[1:0] ALE RST RSTOUT ≥ ≤ 500 ns not transparent not t. transparent not transparent not t. not transparent 1024 TCL At this time RSTF is sampled HIGH WDT Reset is flagged in WDTCON ...

Page 124

... TCL Figure 39. The RSTIN pin provides an internal pull-up (C0) with a pull-up resistor R0 between RPD pin SS ST10F276Z5 ≥ ≤ 500 ns not t. not t. 8 TCL At this time RSTF is sampled LOW so HW Reset is entered , SS ...

Page 125

... RPD pin. On power-up, the logical low level on RPD pin RSTOUT RSTIN + RPD + ST10F276Z5 C0 Figure 37 is not adequate when the RSTIN pin is driven from after the end of the internal reset IL System reset External Hardware a) Hardware Reset b) For Power-up ...

Page 126

... EINIT Instruction Clr Q Set Reset State Machine Clock SRST instruction Trigger watchdog overflow Clr Reset Sequence (512 CPU Clock Cycles) Asynchronous Reset From/to Exit Powerdown Circuit ST10F276Z5 External Reset Source RSTOUT V DD BDRSTEN V DD Weak Pulldown (~200µA) RSTIN ...

Page 127

... ST10F276Z5 19.8 Reset application examples Next two timing diagrams bidirectional internal reset events (Software and Watchdog) including in particular the external capacitances charge and discharge transients (refer also to external circuit scheme). Figure 40. Example of software or watchdog bidirectional reset ( (Figure 40 and Figure 41) provides additional examples of ...

Page 128

... System reset Figure 41. Example of software or watchdog bidirectional reset ( 128/239 ST10F276Z5 ...

Page 129

... ST10F276Z5 19.9 Reset summary A summary of the different reset events is reported in the table below. Table 62. Reset event Event Asynch. Power-on Reset Asynch Asynch Asynch. Hardware Reset (Asynchronous Asynch Asynch Synch Synch. Short Hardware ...

Page 130

... PORT0 latched in RP0H, SYSCON ST10F276Z5 WDTCON Flags max Section 19.3 for details). PORT0 ...

Page 131

... ST10F276Z5 Figure 42. PORT0 bits latched into the different registers after reset H.7 H.6 CLKCFG RP0H CLKCFG Clock Generator P0L.7 ROMEN 10 9 PORT0 H.5 H.4 H.3 H.2 H.1 H.0 L.7 SALSEL CSSEL WRC BUSTYP CSSEL WRC SALSEL Port 4 Port 6 Logic Logic P0L.7 SYSCON BYTDIS WRCFG L.6 L.5 L.4 L.3 L.2 L.1 L.0 BSL Res. ADP EMU Bootstrap Loader ...

Page 132

... Power reduction modes Three different power reduction modes with different levels of power reduction have been implemented in the ST10F276Z5. In Idle mode only CPU is stopped, while peripheral still operate. In Power-down mode both CPU and peripherals are stopped. In Standby mode the main power supply (V ...

Page 133

... A dedicated embedded low-power voltage regulator is implemented to generate the internal low voltage supply (about 1. Standby mode) to bias all those circuits that shall remain active: the portion of XRAM (16Kbytes for the ST10F276Z5), the RTC counters and 32 kHz on-chip oscillator amplifier. Chapter 19: System ...

Page 134

... XRAM2EN set, the RAM Supply switching circuit is not active: in case of a temporary drop on internal V no spurious Standby mode switching can occur (the RAM is not frozen and can still be accessed). The ST10F276Z5 core module, generating the RAM control signals, is powered by internal V supply; during turning off transient these control signals follow the V 18 ...

Page 135

... ST10F276Z5 Warning: 20.3.2 Exiting Standby mode After the system has entered the Standby mode, the procedure to exit this mode consists of a standard Power-on sequence, with the only difference that the RAM is already powered through V internal reference (derived from V 18SB It is recommended to held the device under RESET (RSTIN pin forced low) until external V voltage pin is stable ...

Page 136

... ST10F276Z5 summary, a summary of the different off run off biased on run on biased off off off biased on on off biased on off on biased off off off biased ...

Page 137

... ST10F276Z5 21 Programmable output clock divider A specific register mapped on the XBUS allows to choose the division factor on the CLKOUT signal (P3.15). This register is mapped on X-Miscellaneous memory address range. When CLKOUT function is enabled by setting bit CLKEN of register SYSCON, by default the CPU clock is output on P3.15. Setting bit XMISCEN of register XPERCON and bit XPEN of register SYSCON possible to program the clock prescaling factor: in this way on P3 ...

Page 138

... Register set 22 Register set This section summarizes all registers implemented in the ST10F276Z5, and explains the description format used in the chapters to describe the function and layout of the SFRs. For easy reference, the registers (except for GPRs) are sorted in two ways: ● Sorted by address, to check which register is referenced by a given address. ...

Page 139

... ST10F276Z5 22.2 General purpose registers (GPRs) The GPRs form the register bank that the CPU works with. This register bank may be located anywhere within the internal RAM via the Context Pointer (CP). Due to the addressing mechanism, GPR banks reside only within the internal RAM. All GPRs are bit- addressable ...

Page 140

... CPU general purpose (byte) register RH5 FCh CPU general purpose (byte) register RL6 FDh CPU general purpose (byte) register RH6 FEh CPU general purpose (byte) register RL7 FFh CPU general purpose (byte) register RH7 ST10F276Z5 Reset Description value UUh UUh UUh UUh UUh ...

Page 141

... Special function registers ordered by name The following table lists in alphabetical order all SFRs which are implemented in the ST10F276Z5. Bit-addressable SFRs are marked with the letter “b” in column “Name”. SFRs within the Extended SFR-Space (ESFRs) are marked with the letter “E” in column “ ...

Page 142

... CAPCOM register 24 CAPCOM register 24 interrupt control register 39h CAPCOM register 25 CAPCOM register 25 interrupt control register 3Ah CAPCOM register 26 CAPCOM register 26 interrupt control register 3Bh CAPCOM register 27 CAPCOM register 27 interrupt control register ST10F276Z5 Reset value 0000h - - 00h 0000h - - 00h 0000h - - 00h 0000h - - 00h ...

Page 143

... ST10F276Z5 Table 68. Special function registers ordered by address (continued) Physical Name address CC28 FE78h CC28IC b F178h E BCh CC29 FE7Ah CC29IC b F184h E C2h CC2IC b FF7Ch CC3 FE86h CC30 FE7Ch CC30IC b F18Ch E C6h CC31 FE7Eh CC31IC b F194h E CAh CC3IC b FF7Eh CC4 FE88h CC4IC b FF80h ...

Page 144

... CPU multiply divide register – Low word EDh MAC unit repeat word EFh MAC unit status word Port2 open drain control register Port3 open drain control register Port4 open drain control register ST10F276Z5 Reset value - - 00h - - 00h - - 00h - - 00h 0000h 0000h ...

Page 145

... ST10F276Z5 Table 68. Special function registers ordered by address (continued) Physical Name address ODP6 b F1CEh E E7h ODP7 b F1D2h E E9h ODP8 b F1D6h E EBh ONES b FF1Eh P0H b FF02h P0L b FF00h P1H b FF06h P1L b FF04h P2 b FFC0h P3 b FFC4h P4 b FFC8h P5 b FFA2h P5DIDIS b FFA4h P6 b FFCCh ...

Page 146

... SSC transmit interrupt control register 0Ah CPU stack overflow pointer register 0Bh CPU stack underflow pointer register 89h CPU system configuration register 28h CAPCOM timer 0 register A8h CAPCOM timer 0 and timer 1 control register ST10F276Z5 Reset value 0000h 0000h 0000h 0000h 0000h 0000h - - 00h 0000h ...

Page 147

... ST10F276Z5 Table 68. Special function registers ordered by address (continued) Physical Name address T0IC b FF9Ch T0REL FE54h T1 FE52h T1IC b FF9Eh T1REL FE56h T2 FE40h T2CON b FF40h T2IC b FF60h T3 FE42h T3CON b FF42h T3IC b FF62h T4 FE44h T4CON b FF44h T4IC b FF64h T5 FE46h T5CON b FF46h T5IC b FF66h T6 FE48h ...

Page 148

... Special function registers ordered by address The following table lists by order of their physical addresses all SFRs which are implemented in the ST10F276Z5. Bit-addressable SFRs are marked with the letter “b” in column “Name”. SFRs within the Extended SFR-Space (ESFRs) are marked with the letter “E” in column “ ...

Page 149

... ST10F276Z5 Table 69. Special function registers ordered by address (continued) Physical Name address IDMANUF F07Eh E ADDAT2 F0A0h E SSCTB F0B0h E SSCRB F0B2h E SSCBR F0B4h E DP0L b F100h E DP0H b F102h E DP1L b F104h E DP1H b F106h E RP0H b F108h E CC16IC b F160h E CC17IC b F162h E CC18IC b F164h E CC19IC b F166h E CC20IC b F168h E ...

Page 150

... PWM module pulse width register 2 1Bh PWM module pulse width register 3 20h GPT1 timer 2 register 21h GPT1 timer 3 register 22h GPT1 timer 4 register 23h GPT2 timer 5 register ST10F276Z5 Reset value - - 00h 0000h 0000h - - 00h 0000h - - 00h - - 00h - - 00h - - 00h 0000h ...

Page 151

... ST10F276Z5 Table 69. Special function registers ordered by address (continued) Physical Name address T6 FE48h CAPREL FE4Ah T0 FE50h T1 FE52h T0REL FE54h T1REL FE56h MAL FE5Ch MAH FE5Eh CC16 FE60h CC17 FE62h CC18 FE64h CC19 FE66h CC20 FE68h CC21 FE6Ah CC22 FE6Ch CC23 FE6Eh CC24 ...

Page 152

... CPU multiply divide control register 88h CPU program status word 89h CPU system configuration register 8Ah Bus configuration register 1 8Bh Bus configuration register 2 8Ch Bus configuration register 3 8Dh Bus configuration register 4 ST10F276Z5 Reset value 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h ...

Page 153

... ST10F276Z5 Table 69. Special function registers ordered by address (continued) Physical Name address ZEROS b FF1Ch ONES b FF1Eh T78CON b FF20h CCM4 b FF22h CCM5 b FF24h CCM6 b FF26h CCM7 b FF28h PWMCON0 b FF30h PWMCON1 b FF32h T2CON b FF40h T3CON b FF42h T4CON b FF44h T5CON b FF46h T6CON b FF48h T01CON b FF50h ...

Page 154

... Port 3 register E3h Port 3 direction control register E4h Port 4 register (8-bit) E5h Port 4 direction control register E6h Port 6 register (8-bit) E7h Port 6 direction control register E8h Port 7 register (8-bit) ST10F276Z5 Reset value - - 00h - - 00h - - 00h - - 00h - - 00h - - 00h - - 00h - - 00h - - 00h - - 00h ...

Page 155

... FFDEh 22.5 X-registers sorted by name The following table lists by order of their names all X-Bus registers which are implemented in the ST10F276Z5. Although also physically mapped on X-Bus memory space, the Flash control registers are listed in a separate section,. Note: The X-registers are not bit-addressable. ...

Page 156

... EE22h CAN2: IF1 data B 1 EE24h CAN2: IF1 data B 2 EE14h CAN2: IF1 mask 1 EE16h CAN2: IF1 mask 2 EE1Ch CAN2: IF1 message control EE48h CAN2: IF2 arbitration 1 ST10F276Z5 Reset value 0000h 0000h 0000h 0000h FFFFh FFFFh 0000h 0000h 0000h 0000h 0000h ...

Page 157

... ST10F276Z5 Table 70. X-Registers ordered by name (continued) Name CAN2IF2A2 CAN2IF2CM CAN2IF2CR CAN2IF2DA1 CAN2IF2DA2 CAN2IF2DB1 CAN2IF2DB2 CAN2IF2M1 CAN2IF2M2 CAN2IF2MC CAN2IP1 CAN2IP2 CAN2IR CAN2MV1 CAN2MV2 CAN2ND1 CAN2ND2 CAN2SR CAN2TR CAN2TR1 CAN2TR2 I2CCCR1 I2CCCR2 I2CCR I2CDR I2COAR1 I2COAR2 I2CSR1 I2CSR2 RTCAH RTCAL RTCCON RTCDH RTCDL ...

Page 158

... XPWM module period register 0 EC22h XPWM module period register 1 EC24h XPWM module period register 2 EC26h XPWM module period register 3 EC10h XPWM module up/down counter 0 EC12h XPWM module up/down counter 1 ST10F276Z5 Reset value XXXXh XXXXh XXXXh XXXXh - - 00h XXXXh XXXXh XXXXh XXXXh ...

Page 159

... ST10F276Z5 Table 70. X-Registers ordered by name (continued) Name XPT2 XPT3 XPW0 XPW1 XPW2 XPW3 XPWMCON0 XPWMCON0CLR XPWMCON0SET XPWMCON1 XPWMCON1CLR XPWMCON1SET XPWMPORT XS1BG XS1CON XS1CONCLR XS1CONSET XS1PORT XS1RBUF XS1TBUF XSSCBR XSSCCON XSSCCONCLR XSSCCONSET XSSCPORT XSSCRB XSSCTB Physical Description address EC14h XPWM module up/down counter 2 ...

Page 160

... X-registers ordered by address The following table lists by order of their physical addresses all X-Bus registers which are implemented in the ST10F276Z5. Although also physically mapped on X-Bus memory space, the Flash control registers are listed in a separate section, . Note: The X-registers are not bit-addressable. ...

Page 161

... ST10F276Z5 Table 71. X-registers ordered by address (continued) Name XPICON XIR2SEL XIR2SET XIR2CLR XP1DIDIS XIR3SEL XIR3SET XIR3CLR XMISC XEMU0 XEMU1 XEMU2 XEMU3 XPEREMU XPWMCON0 XPWMCON1 XPOLAR XPWMCON0SET XPWMCON0CLR XPWMCON1SET XPWMCON1CLR XPT0 XPT1 XPT2 XPT3 XPP0 XPP1 XPP2 XPP3 XPW0 Physical Description address Extended port input threshold control ...

Page 162

... CAN2: IF1 data A 2 EE22h CAN2: IF1 data B 1 EE24h CAN2: IF1 data B 2 EE40h CAN2: IF2 command request EE42h CAN2: IF2 command mask EE44h CAN2: IF2 mask 1 ST10F276Z5 Reset value 0000h 0000h 0000h 0000h 000Xh XXXXh XXXXh XXXXh XXXXh XXXXh ...

Page 163

... ST10F276Z5 Table 71. X-registers ordered by address (continued) Name CAN2IF2M2 CAN2IF2A1 CAN2IF2A2 CAN2IF2MC CAN2IF2DA1 CAN2IF2DA2 CAN2IF2DB1 CAN2IF2DB2 CAN2TR1 CAN2TR2 CAN2ND1 CAN2ND2 CAN2IP1 CAN2IP2 CAN2MV1 CAN2MV2 CAN1CR CAN1SR CAN1EC CAN1BTR CAN1IR CAN1TR CAN1BRPER CAN1IF1CR CAN1IF1CM CAN1IF1M1 CAN1IF1M2 CAN1IF1A1 CAN1IF1A2 CAN1IF1MC CAN1IF1DA1 CAN1IF1DA2 CAN1IF1DB1 CAN1IF1DB2 ...

Page 164

... CAN1: transmission request 2 EF90h CAN1: new data 1 EF92h CAN1: new data 2 EFA0h CAN1: interrupt pending 1 EFA2h CAN1: interrupt pending 2 EFB0h CAN1: message valid 1 EFB2h CAN1: message valid 2 ST10F276Z5 Reset value 0001h 0000h FFFFh FFFFh 0000h 0000h 0000h 0000h 0000h 0000h 0000h ...

Page 165

... ST10F276Z5 22.7 Flash registers ordered by name The following table lists by order of their names all FLASH control registers which are implemented in the ST10F276Z5. Note that as they are physically mapped on the X-Bus, these registers are not bit-addressable. Table 72. Flash registers ordered by name Name FARH ...

Page 166

... Register set 22.8 Flash registers ordered by address The following table lists by order of their physical addresses all FLASH control registers which are implemented in the ST10F276Z5. Note that as they are physically mapped on the X-Bus, these registers are not bit-addressable. Table 73. FLASH registers ordered by address ...

Page 167

... ST10F276Z5 22.9 Identification registers The ST10F276Z5 has four Identification registers, mapped in ESFR space. These registers contain: ● The manufacturer identifier ● The chip identifier with revision number ● The internal Flash and size identifier ● the programming voltage description IDMANUF (F07Eh / 3Fh) ...

Page 168

... IDPROG description Bit Programming VDD voltage VDD voltage when programming EPROM or FLASH devices is calculated using PROGVDD the following formula: VDD = 20 x [PROGVDD] / 256 (volts) - 40h for ST10F276Z5 (5 V). PROGVPP Programming VPP voltage (no need of external VPP) - 00h Note: All identification words are read-only registers. ...

Page 169

... ST10F276Z5 22.10 System configuration registers The ST10F276Z5 registers are used for a different configuration of the overall system. These registers are described below. SYSCON (FF12h / 89h ROM STKSZ Note: SYSCON Reset Value is: 0000 0xx0 0x00 0000b . Table 79. SYSCON description Bit XBUS peripheral share mode control ‘ ...

Page 170

... SFR BUSACT2 ALECTL2 - SFR BUSACT3 ALECTL3 - ST10F276Z5 Reset value: 0xx0h BTYP MTTC0 RWDC0 MCTC Reset value: 0000h BTYP MTTC1 RWDC1 MCTC Reset value: 0000h ...

Page 171

... ST10F276Z5 BUSCON4 (FF1Ah / 8Dh CSWEN4 CSREN4 RDYPOL4 RDYEN4 RW RW Table 80. BUSCON4 description Bit Memory cycle time control (number of memory cycle time wait-states) ’0000’: 15 wait-states (Number of wait-states = 15 - [MCTC]). MCTC . . . ’1111’: No wait-states. Read/Write delay control for BUSCONx RWDCx ‘0’: With read/write delay, the CPU inserts 1 TCL after falling edge of ALE. ...

Page 172

... OSC = CPU OSC = CPU OSC = CPU OSC = CPU OSC ESFR EXI5ES EXI4ES EXI3ES RW RW ST10F276Z5 Reset value: --XXh CLKSEL SALSEL CSSEL R R Function Reset value: 0000h EXI2ES EXI1ES ...

Page 173

... ST10F276Z5 Table 82. EXIxES bit description Bit 00 = Fast external interrupts disabled: Standard mode. EXxIN pin not taken in account for entering/exiting Power-down mode Interrupt on positive edge (rising). Enter Power-down mode if EXiIN = ‘0’, exit if EXxIN = ‘1’ (referred as "high" active level) EXIxES (x=7... Interrupt on negative edge (falling). ...

Page 174

... The on-chip 64 Kbyte XRAM is enabled and can be accessed. 174/239 ESFR XMISC XI2C XSSC XASC - - ST10F276Z5 Function Reset value:- 005h XPWM XFLAS XRTC XRAM2 XRAM1 EN HEN Function 1 ...

Page 175

... ST10F276Z5 Table 86. ESFR description (continued) Bit RTC enable ‘0’: Accesses to the on-chip RTC module are disabled, external access performed. Address range 00’ED00h-00’EDFF is directed to external memory only if XRTCEN CAN1EN, CAN2EN, XASCEN, XSSCEN, XI2CEN, XPWMEN and XMISCEN are ‘0’ also. ...

Page 176

... XMISC XI2C XSSC XASC - - Segment 8 x External memory 0 External memory x Reserved 1 Reserved x IFlash (B1F1) Reset value xxxxh XPWM XFLAS XRTC XRAM2 XRAM1 EN HEN ST10F276Z5 1 0 CAN2 CAN1 ...

Page 177

... ST10F276Z5 22.11 Emulation dedicated registers Four additional registers are implemented for emulation purposes only. Similarly to XPEREMU, they are write-only registers. XEMU0 (EB76h XEMU1 (EB78h XEMU2 (EB7Ah XEMU3 (EB7Ch XBUS XEMU0(15:0) W XBUS XEMU1(15:0) ...

Page 178

... V AREF Value ) - 0 0.5 DD ± +150 2000 Min. Max. 4.5 5 +125 –40 +150 , the input section of DD power supply (in the range of tenth of DD Section 23.7. ST10F276Z5 < the Unit V mA °C V Unit V °C ...

Page 179

... ST10F276Z5 23.3 Power considerations The average chip-junction temperature, T following equation: Where: is the Ambient Temperature in ° Θ is the Package Junction-to-Ambient Thermal Resistance, in °C/ the sum the product of I INT P represents the Power Dissipation on Input and Output Pins; user determined. ...

Page 180

... The parameters listed in the following tables represent the characteristics of the ST10F276Z5 and its demands on the system. Where the ST10F276Z5 logic provides signals with their respective timing characteristics, the symbol “CC” (Controller Characteristics) is included in the “Symbol” column. Where the external system must provide signals with their respective timing characteristics to the device, the symbol “ ...

Page 181

... ST10F276Z5 Table 92. DC characteristics (continued) Symbol Input high voltage (TTL mode (except RSTIN, EA, NMI, RPD, IH XTAL1) Input high voltage (CMOS mode (except RSTIN, EA, NMI, RPD, IHS XTAL1) Input high voltage RSTIN, EA IH1 NMI, RPD Input high voltage XTAL1 ...

Page 182

... V IN (4)(6) (9) (10) (11 °C A (11 °C A (11 ° STBY (11 STBY ST10F276Z5 Limit values Min. Max. – – ±0.2 – – ±0.5 +1.0 – – –0.5 – – ±3.0 – ±5 +5 – –1 50 250 = 2.4 V – –40 = 0.4 V –500 – ...

Page 183

... ST10F276Z5 Table 92. DC characteristics (continued) Symbol Standby supply current I (RTC on, 32 kHz Oscillator on, SB2 main VDD off, VSTBY on) Standby supply current I SB3 (VDD transient condition) 1. This specification is not valid for outputs which are switched to open drain mode. In this case the respective output floats and the voltage is imposed by the external circuitry. ...

Page 184

... Clock Input Alternate Data Input Latch Fast External Interrupt Input Test Mode Flash Sense Amplifier and Column Decoder For Port2 complete structure refer also [MHz] CPU ST10F276Z5 P2.0 CC0IO Output Buffer Figure 44 CC1 CC2 ...

Page 185

... ST10F276Z5 23.6 Flash characteristics = 5 V ± 10 Table 93. Flash characteristics Parameter Word program (32-bit) Double word program (2) (64-bit) Bank 0 program (384K) (double word program) Bank 1 program (128K) (double word program) Bank 2 program (192K) (double word program) Bank 3 program (128K) (double word program) ...

Page 186

... Kbyte (code store) > 20 years - - - ST10F276Z5 Unit Notes 100k cycles µs 30 Min delay between 20 ms two requests µs 170 Data retention time 64 Kbyte (EEPROM emulation) > 20 years > 20 years ...

Page 187

... ST10F276Z5 23.7 A/D converter characteristics = 5 V ± 10 ≤ V ≤ AGND Table 95. A/D converter characteristics Symbol V SR Analog reference voltage AREF V SR Analog ground voltage AGND V SR Analog Input voltage AIN I CC Reference supply current AREF t CC Sample time Conversion time ...

Page 188

... V, V AREF AGND /1024. AREF Figure 47. = 1/2TCL. A complete conversion time CPU Sample Comparison TCL * 120 TCL * 240 TCL * 140 TCL * 280 ST10F276Z5 = 5 guaranteed by DD Extra Total conversion TCL * 28 TCL * 388 TCL * 16 TCL * 436 I OV AREF ...

Page 189

... ST10F276Z5 Table 96. A/D Converter programming (continued) ADCTC ADSTC Note: The total conversion time is compatible with the formula valid for ST10F269, while the meaning of the bit fields ADCTC and ADSTC is no longer compatible: The minimum conversion time is 388 TCL, which at 40 MHz CPU frequency corresponds to 4 ...

Page 190

... VAIN (LSBIDEAL) [LSBIDEAL = VAREF / 1024] ST10F276Z5 Offset error OFS Gain error GE Bisector characteristic (1) Example of an actual transfer curve (2) The ideal transfer curve (3) Differential Nonlinearity Error (DNL) (4) Integral Nonlinearity Error (INL) (5) Center of a step of the actual transfer curve ...

Page 191

... ST10F276Z5 23.7.4 Analog reference pins The accuracy of the A/D converter depends on the accuracy of its analog reference: A noise in the reference results in proportionate error in a conversion. A low pass filter on the A/D converter reference source (supplied through pins V order to clean the signal, minimizing the noise. A simple capacitive bypassing may be suffi- cient in most cases ...

Page 192

... R SW ⋅ ----------------------------------------------------------------------------- - and C are initially charged at the source voltage Figure 47), when the sampling phase is started (A/D switch Voltage Transient ST10F276Z5 in Figure 47), in combination L = 50kΩ of external resistance leads < LSB 2 (refer to the A ∆V < 0.5 LSB τ ...

Page 193

... ST10F276Z5 In particular two different transient periods can be distinguished (see 1. A first and quick charge transfer from the internal capacitances C sampling capacitance C Considering a worst case (since the time constant in reality would be faster) in which C is reported in parallel are in series and the time constant is: ...

Page 194

... RC Filter pole) Sampled signal spectrum ( ----------- = ------------------------------------------------------------ maximum, that is for instance 5 V), assum- A value: F > 2048 conversion Rate from the two charge balance equations ⋅ ST10F276Z5 , so the S ...

Page 195

... ST10F276Z5 23.7.6 Example of external network sizing The following hypothesis is formulated in order to proceed with designing the external net- work on A/D converter input pins: ● Analog signal source bandwidth (f ● Conversion rate (f ● Sampling time (T ● Pin input capacitance (C ● Pin input routing capacitance (C ● ...

Page 196

... V The other conditions to verify are if the time constants of the transients are really and significantly shorter than the sampling period duration T For a complete set of parameters characterizing the ST10F276Z5 A/D converter equivalent circuit, refer to A/D Converter Characteristics table at page 187. 23.8 AC characteristics 23 ...

Page 197

... ST10F276Z5 23.8.2 Definition of internal timing The internal operation of the ST10F276Z5 is controlled by the internal CPU clock f edges of the CPU clock can trigger internal (for example pipeline) or external (for example bus cycles) operations. The specification of the external timing (AC Characteristics) therefore depends on the time between two consecutive edges of the CPU clock, called “TCL”. ...

Page 198

... MHz is half the frequency of f CPU XTAL for any TCL. XTAL ) directly follows the frequency of f CPU ST10F276Z5 Notes Default configuration Direct Drive (oscillator bypassed) (3) CPU clock via prescaler /2, an external crystal or resonator XTAL and the high and low time of f ...

Page 199

... Oscillator Watchdog. If bit OWDDIS is set, then the PLL is switched off. 23.8.6 Oscillator watchdog (OWD) An on-chip watchdog oscillator is implemented in the ST10F276Z5. This feature is used for safety operation with an external crystal oscillator (available only when using direct drive mode with or without prescaler, so the PLL is not used to generate the CPU clock multiplying the frequency of the external crystal oscillator) ...

Page 200

... PLL jitter is negligible. Refer to next 23.8.8 Voltage controlled oscillator The ST10F276Z5 implements a PLL which combines different levels of frequency dividers with a Voltage Controlled Oscillator (VCO) working as frequency multiplier. The following table presents a detailed summary of the internal settings and VCO frequency. Table 98. ...