ST10F276Z5 STMicroelectronics, ST10F276Z5 Datasheet - Page 169

• Manufacturer Part Number: ST10F276Z5
• Description: 16-BIT MICROCONTROLLER WITH MAC UNIT, UP TO 832 KBYTES FLASH MEMORY AND UP TO 68 KBYTES RAM
• Manufacturer: STMicroelectronics

Specifications of ST10F276Z5

• Single Voltage Supply: 5V ±10% (embedded regulator for 1.8 V core supply)

ST10F276Z5
22.10
Note:
System configuration registers
The ST10F276Z5 registers are used for a different configuration of the overall system.
These registers are described below.
SYSCON (FF12h / 89h)
SYSCON Reset Value is: 0000 0xx0 0x00 0000b
Table 79.
XPER-SHARE
VISIBLE
XPEN
BDRSTEN
OWDDIS
PWDCFG
CSCFG
15
.
STKSZ
RW
14
Bit
13
SYSCON description
ROM
RW
12
S1
XBUS peripheral share mode control
‘0’: External accesses to XBUS peripherals are disabled.
‘1’: XRAM1 and XRAM2 are accessible via the external bus during hold mode.
External accesses to the other XBUS peripherals are not guaranteed in terms of
AC timings.
Visible mode control
‘0’: Accesses to XBUS peripherals are done internally.
‘1’: XBUS peripheral accesses are made visible on the external pins.
XBUS peripheral enable bit
‘0’: Accesses to the on-chip X-peripherals and XRAM are disabled.
‘1’: The on-chip X-peripherals are enabled.
Bidirectional reset enable
‘0’: RSTIN pin is an input pin only. SW Reset or WDT Reset have no effect on this
pin.
‘1’: RSTIN pin is a bidirectional pin. This pin is pulled low during internal reset
sequence.
Oscillator watchdog disable control
‘0’: Oscillator Watchdog (OWD) is enabled. If PLL is bypassed, the OWD monitors
XTAL1 activity. If there is no activity on XTAL1 for at least 1 µs, the CPU clock is
switched automatically to PLL’s base frequency (from 750 kHz to 3 MHz).
‘1’: OWD is disabled. If the PLL is bypassed, the CPU clock is always driven by
XTAL1 signal. The PLL is turned off to reduce power supply current.
Power-down mode configuration control
‘0’: Power-down mode can only be entered during PWRDN instruction execution if
NMI pin is low, otherwise the instruction has no effect. To exit Power-down mode,
an external reset must occur by asserting the RSTIN pin.
‘1’: Power-down mode can only be entered during PWRDN instruction execution if
all enabled fast external interrupt EXxIN pins are in their inactive level. Exiting this
mode can be done by asserting one enabled EXxIN pin or with external reset.
Chip select configuration control
‘0’: Latched Chip Select lines, CSx changes 1 TCL after rising edge of ALE.
‘1’: Unlatched Chip Select lines, CSx changes with rising edge of ALE.
SGT
RW
DIS
11
ROM
RW
10
EN
RW
BYT
DIS
9
SFR
RW
CLK
EN
8
CFG
RW
WR
7
Function
CFG
RW
CS
6
PWD
CFG
RW
5
OWD
RW
DIS
4
STEN
BDR
RW
3
Reset value: 0xx0h
XPEN
RW
2
Register set
RW
VISI
BLE
1
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SHARE
XPER-
RW
0