ST10F276Z5 STMicroelectronics, ST10F276Z5 Datasheet - Page 198
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ST10F276Z5
Manufacturer Part Number
ST10F276Z5
Description
16-BIT MICROCONTROLLER WITH MAC UNIT, UP TO 832 KBYTES FLASH MEMORY AND UP TO 68 KBYTES RAM
Manufacturer
STMicroelectronics
Datasheet
1.ST10F276Z5.pdf
(239 pages)
Specifications of ST10F276Z5
Single Voltage Supply
5V ±10% (embedded regulator for 1.8 V core supply)
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Electrical characteristics
23.8.3
23.8.4
23.8.5
198/239
Clock generation modes
The following table associates the combinations of these 3 bits with the respective clock
generation mode.
Table 97.
1. The external clock input range refers to a CPU clock range of 1...64 MHz. Moreover, the PLL usage is
2. The limits on input frequency are 4-12 MHz since the usage of the internal oscillator amplifier is required.
3. The maximum depends on the duty cycle of the external clock signal: When 64 MHz is used, 50% duty
Prescaler operation
When pins P0.15-13 (P0H.7-5) equal ‘001’ during reset, the CPU clock is derived from the
internal oscillator (input clock signal) by a 2:1 prescaler.
The frequency of f
is, the duration of an individual TCL) is defined by the period of the input clock f
The timings listed in the AC Characteristics that refer to TCL can therefore be calculated
using the period of f
Note that if the bit OWDDIS in SYSCON register is cleared, the PLL runs on its free-running
frequency and delivers the clock signal for the Oscillator Watchdog. If bit OWDDIS is set,
then the PLL is switched off.
Direct drive
When pins P0.15-13 (P0H.7-5) equal ‘011’ during reset, the on-chip phase locked loop is
disabled, the on-chip oscillator amplifier is bypassed and the CPU clock is directly driven by
the input clock signal on XTAL1 pin.
The frequency of the CPU clock (f
low time of f
input clock f
1
1
1
1
0
0
0
0
(P0H.7-5)
P0.15-13
limited to 4-12 MHz input frequency range. All configurations need a crystal (or ceramic resonator) to
generate the CPU clock through the internal oscillator amplifier (apart from Direct Drive); on the contrary,
the clock can be forced through an external clock source only in Direct Drive mode (on-chip oscillator
amplifier disabled, so no crystal or resonator can be used).
Also, when the PLL is not used and the CPU clock corresponds to F
must be used: It is not possible to force any clock though an external clock source.
cycle shall be granted (low phase = high phase = 7.8 ns); when 32 MHz is selected, a 25% duty cycle can
be accepted (minimum phase, high or low, again equal to 7.8ns).
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
CPU
XTAL
On-chip clock generator selections
F
F
F
F
F
F
F
F
XTAL
XTAL
XTAL
XTAL
XTAL
XTAL
XTAL
XTAL
f
CPU frequency
.
(that is, the duration of an individual TCL) is defined by the duty cycle of the
CPU
CPU
x 4
x 3
x 8
x 5
x 1
x 10
/ 2
x 16
XTAL
= f
is half the frequency of f
XTAL
for any TCL.
x F
CPU
4 to 8 MHz
5.3 to 10.6 MHz
4 to 8 MHz
6.4 to 12 MHz
1 to 64 MHz
4 to 6.4 MHz
4 to 12 MHz
4 MHz
External clock input
) directly follows the frequency of f
range
(1)(2)
XTAL
and the high and low time of f
Default configuration
Direct Drive (oscillator bypassed)
CPU clock via prescaler
XTAL
/2, an external crystal or resonator
Notes
XTAL
so the high and
(3)
ST10F276Z5
XTAL
CPU
.
(3)
(that
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