ST10F276Z5 STMicroelectronics, ST10F276Z5 Datasheet - Page 171

• Manufacturer Part Number: ST10F276Z5
• Description: 16-BIT MICROCONTROLLER WITH MAC UNIT, UP TO 832 KBYTES FLASH MEMORY AND UP TO 68 KBYTES RAM
• Manufacturer: STMicroelectronics

Specifications of ST10F276Z5

• Single Voltage Supply: 5V ±10% (embedded regulator for 1.8 V core supply)

ST10F276Z5
BUSCON4 (FF1Ah / 8Dh)
Table 80.
1. BTYP (bit 6 and 7) is set according to the configuration of the bit l6 and l7 of PORT0 latched at the end of
CSWEN4 CSREN4 RDYPOL4 RDYEN4
MCTC
RWDCx
MTTCx
BTYP
ALECTLx
BUSACTx
RDYENx
RDYPOLx
CSRENx
CSWENx
RW
15
the reset sequence.
(1)
Bit
RW
14
BUSCON4 description
13
Memory cycle time control (number of memory cycle time wait-states)
’0000’: 15 wait-states (Number of wait-states = 15 - [MCTC]).
. . .
’1111’: No wait-states.
Read/Write delay control for BUSCONx
‘0’: With read/write delay, the CPU inserts 1 TCL after falling edge of ALE.
‘1’: No read/write delay, RW is activated after falling edge of ALE.
Memory tri-state time control
‘0’: 1 wait-state.
‘1’: No wait-state.
External bus configuration
’00’: 8-bit Demultiplexed Bus
’01’: 8-bit Multiplexed Bus
’10’: 16-bit Demultiplexed Bus
’11’: 16-bit Multiplexed Bus
Note: For BUSCON0 BTYP is defined via PORT0 during reset.
ALE lengthening control
‘0’: Normal ALE signal.
‘1’: Lengthened ALE signal.
Bus active control
‘0’: External bus disabled.
‘1’: External bus enabled (within the respective address window, see ADDRSEL).
Ready input enable
‘0’: External bus cycle is controlled by bit field MCTC only.
‘1’: External bus cycle is controlled by the READY input signal.
Ready active level control
‘0’: Active level on the READY pin is low, bus cycle terminates with a ‘0’ on READY
pin.
‘1’: Active level on the READY pin is high, bus cycle terminates with a ‘1’ on
READY pin.
Read chip select enable
‘0’: The CS signal is independent of the read command (RD).
‘1’: The CS signal is generated for the duration of the read command.
Write chip select enable
‘0’: The CS signal is independent of the write command (WR, WRL, WRH).
‘1’: The CS signal is generated for the duration of the write command.
RW
12
11
-
BUSACT4 ALECTL4
RW
10
RW
9
SFR
Function
8
-
7
BTYP
RW
6
MTTC4 RWDC4
RW
5
RW
Reset value: 0000h
4
Register set
3 2 1 0
MCTC
RW
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