ST7260E1 STMicroelectronics, ST7260E1 Datasheet - Page 54
ST7260E1
Manufacturer Part Number
ST7260E1
Description
LOW SPEED USB 8-BIT MCU FAMILY WITH UP TO 8K FLASH/ROM AND SERIAL COMMUNICATION INTERFACE (SCI)
Manufacturer
STMicroelectronics
Datasheet
1.ST7260E2.pdf
(139 pages)
Specifications of ST7260E1
4 Or 8 Kbytes Program Memory
high density Flash (HDFlash), or FastROM with readout and write protection
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Watchdog timer (WDG)
Note:
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1
2
3
4
5
6
After reading the ICiHR register, transfer of input capture data is inhibited and ICFi will never
be set until the ICiLR register is also read.
The ICiR register contains the free running counter value which corresponds to the most
recent input capture.
The two input capture functions can be used together even if the timer also uses the two
output compare functions.
In One pulse mode and PWM mode only Input Capture 2 can be used.
The alternate inputs (ICAP1 and ICAP2) are always directly connected to the timer. So any
transitions on these pins activates the input capture function.
Moreover if one of the ICAPi pins is configured as an input and the second one as an output,
an interrupt can be generated if the user toggles the output pin and if the ICIE bit is set.
This can be avoided if the input capture function i is disabled by reading the ICiHR (see
note 1).
The TOF bit can be used with interrupt generation in order to measure events that go
beyond the timer range (FFFFh).
Figure 29. Input capture block diagram
Figure 30. Input capture timing diagram
ICAP2
ICAP1
pin
pin
Counter register
Note: The rising edge is the active edge.
ICAPi register
16-bit
Timer clock
ICAPi flag
IC2R register
16-bit free running counter
ICAPi pin
Edge Detect
circuit 2
FF01
Edge Detect
circuit 1
IC1R register
FF02
ICF1
ICIE
FF03
ICF2
FF03
(Control register 1) CR1
(Control register 2) CR2
CC1
(Status register) SR
CC0
0
IEDG1
IEDG2
ST7260xx
0
0
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