ST7260E1 STMicroelectronics, ST7260E1 Datasheet - Page 27
ST7260E1
Manufacturer Part Number
ST7260E1
Description
LOW SPEED USB 8-BIT MCU FAMILY WITH UP TO 8K FLASH/ROM AND SERIAL COMMUNICATION INTERFACE (SCI)
Manufacturer
STMicroelectronics
Datasheet
1.ST7260E2.pdf
(139 pages)
Specifications of ST7260E1
4 Or 8 Kbytes Program Memory
high density Flash (HDFlash), or FastROM with readout and write protection
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ST7260xx
Note:
7.3
7.3.1
Figure 12. Reset timing diagram
Refer to Electrical Characteristics for values of t
Clock system
General description
The MCU accepts either a crystal or ceramic resonator, or an external clock signal to drive
the internal oscillator. The internal clock (f
frequency (f
clock used). The internal clock is further divided by 2 by setting the SMS bit in the
Miscellaneous Register.
Using the OSC24/12 bit in the option byte, a 12 MHz or a 24 MHz external clock can be
used to provide an internal frequency of either 2, 4 or 8 MHz while maintaining a 6 MHz for
the USB (refer to
The internal clock signal (f
signal consists of a square wave with a duty cycle of 50%.
The internal oscillator is designed to operate with an AT-cut parallel resonant quartz or
ceramic resonator in the frequency range specified for f
recommended when using a crystal, and
crystal and associated components should be mounted as close as possible to the input
pins in order to minimize output distortion and start-up stabilisation time.
V
OSCIN
f
CPU
DD
RESET
PC
WATCHDOG RESET
OSC
t
DDR
), which is divided by 3 (and by 2 or 4 for USB, depending on the external
t
Figure
OXOV
15).
CPU
) is also routed to the on-chip peripherals. The CPU clock
Table 9
CPU
) is derived from the external oscillator
DDR
lists the recommended capacitance. The
, t
OXOV
4096 CPU
CYCLES
osc
CLOCK
DELAY
, V
. The circuit shown in
IT+
Reset and clock management
FFFE
, V
IT-
and V
FFFF
hys
Figure 14
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