ST7260E1 STMicroelectronics, ST7260E1 Datasheet - Page 135

• Manufacturer Part Number: ST7260E1
• Description: LOW SPEED USB 8-BIT MCU FAMILY WITH UP TO 8K FLASH/ROM AND SERIAL COMMUNICATION INTERFACE (SCI)
• Manufacturer: STMicroelectronics

Specifications of ST7260E1

• 4 Or 8 Kbytes Program Memory: high density Flash (HDFlash), or FastROM with readout and write protection

ST7260xx
19
19.1
19.2
19.3
Known limitations
PA2 limitation with OCMP1 enabled
Description
This limitation affects only Rev B Flash devices (with Internal Sales Type 72F60xxxxx$x7); it
has been corrected in Rev W Flash devices (with Internal Sales Type 72F60xxxxx$x9).
Refer to
When Output Compare 1 function (OCMP1) on pin PA6 is enabled by setting the OC1E bit in
the TCR2 register, pin PA2 is also affected.
In particular, the PA2 pin is forced to be floating even if port configuration (PADDR+PADR)
has set it as output low. However, it can be still used as an input.
Unexpected reset fetch
If an interrupt request occurs while a "POP CC" instruction is executed, the interrupt
controller does not recognise the source of the interrupt and, by default, passes the RESET
vector address to the CPU.
Workaround
To solve this issue, a "POP CC" instruction must always be preceded by a "SIM" instruction.
SCI wrong break duration
Description
A single break character is sent by setting and resetting the SBK bit in the SCICR2 register.
In some cases, the break character may have a longer duration than expected:
●
●
In the same way, as long as the SBK bit is set, break characters are sent to the TDO pin.
This may lead to generate one break more than expected.
Occurrence
The occurrence of the problem is random and proportional to the baudrate. With a transmit
frequency of 19200 baud (f
occurrence is around 1%.
Workaround
If this wrong duration is not compliant with the communication protocol in the application,
software can request that an Idle line be generated before the break character. In this case,
the break duration is always correct assuming the application is not doing anything between
the idle and the break. This can be ensured by temporarily disabling interrupts.
20 bits instead of 10 bits if M=0
22 bits instead of 11 bits if M=1
Figure 69 on page
CPU
137.
=8 MHz and SCIBRR=0xC9), the wrong break duration
Known limitations
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