ST7260E1 STMicroelectronics, ST7260E1 Datasheet - Page 48

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ST7260E1

Manufacturer Part Number
ST7260E1
Description
LOW SPEED USB 8-BIT MCU FAMILY WITH UP TO 8K FLASH/ROM AND SERIAL COMMUNICATION INTERFACE (SCI)
Manufacturer
STMicroelectronics
Datasheet

Specifications of ST7260E1

4 Or 8 Kbytes Program Memory
high density Flash (HDFlash), or FastROM with readout and write protection
Watchdog timer (WDG)
12.4
12.4.1
12.4.2
48/139
16-bit timer
Introduction
The timer consists of a 16-bit free-running counter driven by a programmable prescaler.
It may be used for a variety of purposes, including pulse length measurement of up to two
input signals (input capture) or generation of up to two output waveforms (output compare
and PWM).
Pulse lengths and waveform periods can be modulated from a few microseconds to several
milliseconds using the timer prescaler and the CPU clock prescaler.
Some ST7 devices have two on-chip 16-bit timers. They are completely independent, and
do not share any resources. They are synchronized after a MCU reset as long as the timer
clock frequencies are not modified.
This description covers one or two 16-bit timers. In ST7 devices with two timers, register
names are prefixed with TA (Timer A) or TB (Timer B).
Main features
The timer block diagram is shown in
a. Some timer pins may not be available (not bonded) in some ST7 devices. Refer to
When reading an input signal on a non-bonded pin, the value will always be ‘1’.
Programmable prescaler: f
Overflow status flag and maskable interrupt
External clock input (must be at least four times slower than the CPU clock speed) with
the choice of active edge
1 or 2 output compare functions each with:
1 or 2 input capture functions each with:
Pulse width modulation mode (PWM)
One pulse mode
Reduced power mode
5 alternate functions on I/O ports (ICAP1, ICAP2, OCMP1, OCMP2, EXTCLK)
2 dedicated 16-bit registers
2 dedicated programmable signals
2 dedicated status flags
1 dedicated maskable interrupt
2 dedicated 16-bit registers
2 dedicated active edge selection signals
2 dedicated status flags
1 dedicated maskable interrupt
CPU
divided by 2, 4 or 8
Figure
24.
Section 3: Pin
ST7260xx
description.
(a)

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