ST72324BJ6 STMicroelectronics, ST72324BJ6 Datasheet - Page 57
ST72324BJ6
Manufacturer Part Number
ST72324BJ6
Description
5V RANGE 8-BIT MCU WITH 8 TO 32K FLASH/ROM, 10-BIT ADC, 4 TIMERS, SPI, SCI INTERFACE
Manufacturer
STMicroelectronics
Datasheet
1.ST72324BJ6.pdf
(193 pages)
Specifications of ST72324BJ6
Hdflash Endurance
1 kcycle at 55 °C, data retention 40 years at 85 °C
Clock Sources
crystal/ceramic resonator oscillators, int. RC osc. and ext. clock input
4 Power Saving Modes
Slow, Wait, Active-halt, and Halt
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ST72324Bxx
Halt mode recommendations
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Make sure that an external event is available to wake up the microcontroller from Halt
mode.
When using an external interrupt to wake up the microcontroller, reinitialize the
corresponding I/O as “Input Pull-up with Interrupt” before executing the HALT
instruction. The main reason for this is that the I/O may be wrongly configured due to
external interference or by an unforeseen logical condition.
For the same reason, reinitialize the sensitivity level of each external interrupt as a
precautionary measure.
The opcode for the HALT instruction is 0x8E. To avoid an unexpected HALT instruction
due to a program counter failure, it is advised to clear all occurrences of the data value
0x8E from memory. For example, avoid defining a constant in ROM with the value
0x8E.
As the HALT instruction clears the interrupt mask in the CC register to allow interrupts,
the user may choose to clear all pending interrupt bits before executing the HALT
instruction. This avoids entering other peripheral interrupt routines after executing the
external interrupt routine corresponding to the wakeup event (reset or external
interrupt).
Power saving modes
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