ST72324BJ6 STMicroelectronics, ST72324BJ6 Datasheet - Page 114

• Manufacturer Part Number: ST72324BJ6
• Description: 5V RANGE 8-BIT MCU WITH 8 TO 32K FLASH/ROM, 10-BIT ADC, 4 TIMERS, SPI, SCI INTERFACE
• Manufacturer: STMicroelectronics

Specifications of ST72324BJ6

• Hdflash Endurance: 1 kcycle at 55 °C, data retention 40 years at 85 °C
• Clock Sources: crystal/ceramic resonator oscillators, int. RC osc. and ext. clock input
• 4 Power Saving Modes: Slow, Wait, Active-halt, and Halt

On-chip peripherals
Note:
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Overrun error
An overrun error occurs when a character is received when RDRF has not been reset. Data
can not be transferred from the shift register to the RDR register as long as the RDRF bit is
not cleared.
When a overrun error occurs:
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The OR bit is reset by an access to the SCISR register followed by a SCIDR register read
operation.
Noise error
Oversampling techniques are used for data recovery by discriminating between valid
incoming data and noise. Normal data bits are considered valid if three consecutive samples
(8th, 9th, 10th) have the same bit value, otherwise the NF flag is set. In the case of start bit
detection, the NF flag is set on the basis of an algorithm combining both valid edge
detection and three samples (8th, 9th, 10th). Therefore, to prevent the NF flag from being
set during start bit reception, there should be a valid edge detection as well as three valid
samples.
When noise is detected in a frame:
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The NF flag is reset by a SCISR register read operation followed by a SCIDR register read
operation.
During reception, if a false start bit is detected (for example, 8th, 9th, 10th samples are
011,101,110), the frame is discarded and the receiving sequence is not started for this
frame. There is no RDRF bit set for this frame and the NF flag is set internally (not
accessible to the user). This NF flag is accessible along with the RDRF bit when a next valid
frame is received.
If the application Start bit is not long enough to match the above requirements, then the NF
Flag may get set due to the short Start bit. In this case, the NF flag may be ignored by the
application software when the first valid byte is received.
See also
The OR bit is set.
The RDR content will not be lost.
The shift register will be overwritten.
An interrupt is generated if the RIE bit is set and the I bit is cleared in the CCR register.
The NF flag is set at the rising edge of the RDRF bit.
Data is transferred from the Shift register to the SCIDR register.
No interrupt is generated. However this bit rises at the same time as the RDRF bit
which itself generates an interrupt.
Noise error causes on page
119.
ST72324Bxx