ST72324BJ6 STMicroelectronics, ST72324BJ6 Datasheet - Page 55

• Manufacturer Part Number: ST72324BJ6
• Description: 5V RANGE 8-BIT MCU WITH 8 TO 32K FLASH/ROM, 10-BIT ADC, 4 TIMERS, SPI, SCI INTERFACE
• Manufacturer: STMicroelectronics

Specifications of ST72324BJ6

• Hdflash Endurance: 1 kcycle at 55 °C, data retention 40 years at 85 °C
• Clock Sources: crystal/ceramic resonator oscillators, int. RC osc. and ext. clock input
• 4 Power Saving Modes: Slow, Wait, Active-halt, and Halt

ST72324Bxx
8.4.2
Figure 27. Active-halt mode flowchart
1. Peripheral clocked with an external clock source can still be active.
2. Only the MCC/RTC interrupt and some specific interrupts can exit the MCU from Active-halt mode (such as
3. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are
Halt mode
The Halt mode is the lowest power consumption mode of the MCU. It is entered by
executing the ‘HALT’ instruction when the OIE bit of the Main Clock Controller Status
register (MCCSR) is cleared (see
and beeper (MCC/RTC) on page 69
The MCU can exit Halt mode on reception of either a specific interrupt (see
Interrupt
the oscillator is immediately turned on and the 256 or 4096 CPU cycle delay is used to
stabilize the oscillator. After the start up delay, the CPU resumes operation by servicing the
interrupt or by fetching the reset vector which woke it up (see
When entering Halt mode, the I[1:0] bits in the CC register are forced to ‘10b’ to enable
interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately.
In Halt mode, the main oscillator is turned off causing all internal processing to be stopped,
including the operation of the on-chip peripherals. All peripherals are not clocked except the
ones which get their clock supply from another clock generator (such as an external or
auxiliary oscillator).
The compatibility of Watchdog operation with Halt mode is configured by the “WDGHALT”
option bit of the option byte. The HALT instruction when executed while the Watchdog
system is enabled, can generate a Watchdog reset (see
details.
external interrupt). Refer to
set to the current software priority level of the interrupt routine and restored when the CC register is
popped.
mapping) or a reset. When exiting Halt mode by means of a reset or an interrupt,
Table 25: Interrupt mapping on page 51
N
(MCCSR.OIE = 1)
Halt instruction
Section 10.2: Main clock controller with real-time clock
Interrupt
Y
for more details on the MCCSR register).
(2)
256 or 4096 CPU clock
Oscillator
Peripherals
Oscillator
Peripherals
Oscillator
Peripherals
CPU
I[1:0] bits
CPU
I[1:0] bits
CPU
I[1:0] bits
N
Fetch reset vector
or service interrupt
cycle delay
Y
Reset
(1)
Section 14.1 on page
for more details.
XX
XX
on
off
on
on
on
on
10
on
off
off
(3)
(3)
Figure
29).
Power saving modes
Table 25:
179) for more
55/193