ST7DALIF2 STMicroelectronics, ST7DALIF2 Datasheet - Page 85

• Manufacturer Part Number: ST7DALIF2
• Description: 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, TIMERS, SPI
• Manufacturer: STMicroelectronics

Specifications of ST7DALIF2

• 8 Kbytes Single Voltage Flash Program Memory With Read-out Protection, In-circuit Programming And In-application Programming (icp And Iap). 10k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55°C.
• 256 Bytes Data Eeprom With Read-out Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55°C.
• Clock Sources: Internal 1% RC oscillator, crystal/ceramic resonator or external clock
• Five Power Saving Modes: Halt, Active-Halt, Wait and Slow, Auto Wake Up From Halt

ST7DALIF2
15.3
15.3.1
15.3.2
15.3.3
Functional description
Timebase counter 1
The 8-bit value of Counter 1 cannot be read or written by software. After an MCU reset, it
starts incrementing from 0 at a frequency of f
counter rolls over from F9h to 00h. If f
counter overflow events is 1 ms. This period can be doubled by setting the TB bit in the
LTCSR1 register.
When Counter 1 overflows, the TB1F bit is set by hardware and an interrupt request is
generated if the TB1IE bit is set. The TB1F bit is cleared by software reading the LTCSR1
register.
Input capture
The 8-bit input capture register is used to latch the free-running upcounter (Counter 1) 1
after a rising or falling edge is detected on the LTIC pin. When an input capture occurs, the
ICF bit is set and the LTICR1 register contains the MSB of Counter 1. An interrupt is
generated if the ICIE bit is set. The ICF bit is cleared by reading the LTICR register.
The LTICR is a read-only register and always contains the data from the last input capture.
Input capture is inhibited if the ICF bit is set.
Timebase counter 2
Counter 2 is an 8-bit autoreload upcounter. It can be read by accessing the LTCNTR
register. After an MCU reset, it increments at a frequency of f
stored in the LTARR register. A counter overflow event occurs when the counter rolls over
from FFh to the LTARR reload value. Software can write a new value at anytime in the
LTARR register, this value will be automatically loaded in the counter when the next overflow
occurs.
When Counter 2 overflows, the TB2F bit in the LTCSR2 register is set by hardware and an
interrupt request is generated if the TB2IE bit is set. The TB2F bit is cleared by software
reading the LTCSR2 register.
Figure 40. Input capture timing diagram.
LTICR REGISTER
8-bit COUNTER 1
ICF FLAG
LTIC PIN
f
OSC2
f
CPU
/32
01h
(@ 8MHz f
4µs
02h
xxh
OSC2
)
03h
OSC2
04h
= 8 MHz, then the time period between two
05h
OSC2
04h
/32. An overflow event occurs when the
06h
07h
OSC2
/32 starting from the value
LTIC REGISTER
07h
CLEARED
READING
BY S/W
t
Lite timer 2 (LT2)
85/171