ST7DALIF2 STMicroelectronics, ST7DALIF2 Datasheet - Page 78

• Manufacturer Part Number: ST7DALIF2
• Description: 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, TIMERS, SPI
• Manufacturer: STMicroelectronics

Specifications of ST7DALIF2

• 8 Kbytes Single Voltage Flash Program Memory With Read-out Protection, In-circuit Programming And In-application Programming (icp And Iap). 10k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55°C.
• 256 Bytes Data Eeprom With Read-out Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55°C.
• Clock Sources: Internal 1% RC oscillator, crystal/ceramic resonator or external clock
• Five Power Saving Modes: Halt, Active-Halt, Wait and Slow, Auto Wake Up From Halt

12-bit autoreload timer 2 (AT2)
14.6.2
14.6.3
78/171
Bits 4:3 = CK[1:0] Counter Clock Selection.
These bits are set and cleared by software and cleared by hardware after a reset. They
select the clock frequency of the counter.
Table 38.
1. PWM mode and Output Compare modes are not available at this frequency.
2. ATICR counter may return inaccurate results when read. It is therefore not recommended to use Input
Bit 2 = OVF Overflow Flag.
This bit is set by hardware and cleared by software by reading the TCSR register. It
indicates the transition of the counter from FFFh to ATR value.
0: No counter overflow occurred
1: Counter overflow occurred
Bit 1 = OVFIE Overflow Interrupt Enable.
This bit is read/write by software and cleared by hardware after a reset.
0: OVF interrupt disabled.
1: OVF interrupt enabled.
Bit 0 = CMPIE Compare Interrupt Enable.
This bit is read/write by software and cleared by hardware after a reset. It can be used to
mask the interrupt generated when the CMPF bit is set.
0: CMPF interrupt disabled.
1: CMPF interrupt enabled.
Counter register high (CNTRH)
Read only
Reset Value: 0000 0000 (000h)
Counter register low (CNTRL)
Read only
Reset Value: 0000 0000 (000h)
Bits 15:12 = Reserved.
Bits 11:0 = CNTR[11:0] Counter Value.
This 12-bit register is read by software and cleared by hardware after a reset. The counter is
incremented continuously as soon as a counter clock is selected. To obtain the 12-bit value,
CNTR7
Capture mode at this frequency.
15
0
7
Counter clock frequency
CNTR6
0
f
LTIMER
Counter clock selection
(1 ms timebase @ 8 MHz)
CNTR5
0
32 MHz
OFF
f
CPU
(2)
CNTR4
0
CNTR3
(1)
CNTR
11
CNTR2
CNTR
10
CNTR9
CNTR1
CK1
0
0
1
1
ST7DALIF2
CNTR8
CNTR0
CK0
0
1
0
1
8
0