ST7DALIF2 STMicroelectronics, ST7DALIF2 Datasheet - Page 108

• Manufacturer Part Number: ST7DALIF2
• Description: 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, TIMERS, SPI
• Manufacturer: STMicroelectronics

Specifications of ST7DALIF2

• 8 Kbytes Single Voltage Flash Program Memory With Read-out Protection, In-circuit Programming And In-application Programming (icp And Iap). 10k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55°C.
• 256 Bytes Data Eeprom With Read-out Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55°C.
• Clock Sources: Internal 1% RC oscillator, crystal/ceramic resonator or external clock
• Five Power Saving Modes: Halt, Active-Halt, Wait and Slow, Auto Wake Up From Halt

Serial peripheral interface (SPI)
17.5
17.5.1
Note:
Caution:
108/171
Figure 51. Single master / multiple slave configuration
Low power modes
Table 46.
Using the SPI to wake-up the device from Halt mode
In slave configuration, the SPI is able to wake-up the
interrupt. The data received is subsequently read from the SPIDR register when the
software is running (interrupt vector fetch). If multiple data transfers have been performed
before software clears the SPIF bit, then the OVR bit is set by hardware.
When waking up from Halt mode, if the SPI remains in Slave mode, it is recommended to
perform an extra communications cycle to bring the SPI from Halt mode state to normal
state. If the SPI exits from Slave mode, it returns to normal state immediately.
The SPI can wake-up the
pin or the SSI bit in the SPICSR register) is low when the
selection is configured as external (see
level on the SS pin when the slave enters Halt mode.
5V
Mode
Wait
Halt
MOSI
SS
SCK
SCK
MOSI
Effect of low power modes on SPI
Device
Master
Device
Slave
MISO
MISO
SS
No effect on SPI.
SPI interrupt events cause the Device to exit from Wait mode.
SPI registers are frozen.
In Halt mode, the SPI is inactive. SPI operation resumes when the Device is
woken up by an interrupt with “exit from Halt mode” capability. The data received
is subsequently read from the SPIDR register when the software is running
(interrupt vector fetching). If several data are received before the wake-up event,
then an overrun error is generated. This error can be detected after the fetch of
the interrupt routine that woke up the Device.
Device
MOSI
SCK
from Halt mode only if the Slave Select signal (external SS
Device
Slave
MISO
SS
Section
17.4.1), make sure the master drives a low
MOSI
SCK
Description
Device
Slave
Device
MISO
SS
Device
from Halt mode through a SPIF
enters Halt mode. So if Slave
MOSI
SCK
Device
Slave
MISO
SS
ST7DALIF2