ST7DALIF2 STMicroelectronics, ST7DALIF2 Datasheet - Page 103

• Manufacturer Part Number: ST7DALIF2
• Description: 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, TIMERS, SPI
• Manufacturer: STMicroelectronics

Specifications of ST7DALIF2

• 8 Kbytes Single Voltage Flash Program Memory With Read-out Protection, In-circuit Programming And In-application Programming (icp And Iap). 10k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55°C.
• 256 Bytes Data Eeprom With Read-out Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55°C.
• Clock Sources: Internal 1% RC oscillator, crystal/ceramic resonator or external clock
• Five Power Saving Modes: Halt, Active-Halt, Wait and Slow, Auto Wake Up From Halt

ST7DALIF2
17.4.2
Note:
Note:
Note:
Note:
Figure 48. Hardware/software slave select management
Master mode operation
In master mode, the serial clock is output on the SCK pin. The clock frequency, polarity and
phase are configured by software (refer to the description of the SPICSR register).
The idle state of SCK must correspond to the polarity selected in the SPICSR register (by
pulling up SCK if CPOL=1 or pulling down SCK if CPOL=0).
How to operate the SPI in master mode
To operate the SPI in master mode, perform the following steps in order (if the SPICSR
register is not written first, the SPICR register setting (MSTR bit) may be not taken into
account):
1.
The slave must have the same CPOL and CPHA settings as the master.
2.
3.
MSTR and SPE bits remain set only if SS is high.
Important: if the SPICSR register is not written first, the SPICR register setting (MSTR bit)
may be not taken into account.
The transmit sequence begins when software writes a byte in the SPIDR register.
Master mode transmit sequence
When software writes to the SPIDR register, the data byte is loaded into the 8-bit shift
register and then shifted out serially to the MOSI pin most significant bit first.
When data transfer is complete:
Clearing the SPIF bit is performed by the following software sequence:
1.
2.
– Select the clock frequency by configuring the SPR[2:0] bits.
– Select the clock polarity and clock phase by configuring the CPOL and CPHA bits.
– Either set the SSM bit and set the SSI bit or clear the SSM bit and tie the SS pin high
– Set the MSTR and SPE bits
– The SPIF bit is set by hardware
– An interrupt request is generated if the SPIE bit is set and the interrupt mask in the
Write to the SPICR register:
Write to the SPICSR register:
Write to the SPICR register:
An access to the SPICSR register while the SPIF bit is set
A read to the SPIDR register.
Figure 49
for the complete byte transmit sequence.
CCR register is cleared.
shows the four possible configurations.
SS external pin
SSI bit
SSM bit
1
0
SS internal
Serial peripheral interface (SPI)
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