ST7DALIF2 STMicroelectronics, ST7DALIF2 Datasheet
ST7DALIF2
Specifications of ST7DALIF2
Related parts for ST7DALIF2
ST7DALIF2 Summary of contents
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... Instruction set – 8-bit data manipulation – 63 basic instructions with illegal opcode detection – 17 main addressing modes – unsigned multiply instructions ■ Development tools – Full hardware/software development package – DM (Debug module) Rev 3 ST7DALIF2 SO20 300” 1/171 www.st.com 171 ...
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... Data EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.3 Memory access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.4 Power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.5 Access error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.6 Data EEPROM readout protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.7 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.8 EEPROM control/status register (EECSR 2/171 In-circuit programming (ICP application programming (IAP Readout protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Flash write/erase protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Flash control/status register (FCSR ST7DALIF2 ...
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... ST7DALIF2 8 Central processing unit (CPU 8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8.3 CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8.3.1 8.3.2 8.3.3 8.3.4 8.3.5 9 Supply, reset and clock management . . . . . . . . . . . . . . . . . . . . . . . . . . 32 9.1 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 9.2 Internal RC oscillator adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 9.3 Phase locked loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9.4 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 9.4.1 9.4.2 9.5 Multi-oscillator (MO 9.6 Reset sequence manager (RSM 9.6.1 9.6.2 9.6.3 9.6.4 9.6.5 9.7 System integrity management (SI 9.7.1 9.7.2 9.7.3 9.7.4 10 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 10.1 Non maskable software interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 10 ...
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... Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 13.4 Hardware watchdog option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 13.4.1 13.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 13.6 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 13.6.1 4/171 External interrupt control register (EICR External interrupt selection register (EISR Halt mode recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Input modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Using Halt mode with the WDG (WDGHALT option Control register (CR ST7DALIF2 ...
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... ST7DALIF2 14 12-bit autoreload timer 2 (AT2 14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 14.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 14.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 14.3.1 14.3.2 14.3.3 14.3.4 14.4 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 14.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 14.6 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 14.6.1 14.6.2 14.6.3 14.6.4 14.6.5 14.6.6 14.6.7 14.6.8 14.6.9 14.6.10 PWMx duty cycle register low (DCRxL 14.6.11 Input capture register high (ATICRH 14.6.12 Input capture register low (ATICRL 14.6.13 Transfer control register (TRANCR Lite timer 2 (LT2 15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 15 ...
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... Lite timer autoreload register (LTARR Lite timer counter 2 (LTCNTR Lite timer control/status register (LTCSR1 Lite timer input capture register (LTICR Forced transmission (test mode Normal transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 DCM enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Slave select management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Master mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Slave mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 ST7DALIF2 ...
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... ST7DALIF2 17.4.4 17.4.5 17.4.6 17.5 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 17.5.1 17.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 17.7 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 17.7.1 17.7.2 17.7.3 18 10-bit A/D converter (ADC 113 18.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 18.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 18.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 18.3.1 18.3.2 18.3.3 18.3.4 18.4 Changing the conversion channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 18.5 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 18.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 18.7 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 18.7.1 18.7.2 18.7.3 19 Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 19.1 CPU addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 19 ...
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... Operating conditions with low voltage detector (LVD 131 Auxiliary Voltage Detector (AVD) Thresholds . . . . . . . . . . . . . . . . . . . 131 Internal RC oscillator and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Supply current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Crystal and ceramic resonator oscillators . . . . . . . . . . . . . . . . . . . . . . 138 Functional EMS (electromagnetic susceptibility 141 Electromagnetic interference (EMI 142 Absolute maximum ratings (electrical sensitivity 142 General characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 ST7DALIF2 ...
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... ST7DALIF2 22.1.1 22.1.2 22.2 Device ordering information and transfer of customer code . . . . . . . . . . 164 23 Important notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 23.1 Execution of BTJX instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 23.2 ADC conversion spurious results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 23 converter accuracy for first conversion . . . . . . . . . . . . . . . . . . . . . . 166 23.4 Negative injection impact on ADC accuracy . . . . . . . . . . . . . . . . . . . . . 166 23.5 Clearing active interrupts outside interrupt routine . . . . . . . . . . . . . . . . . 166 23 ...
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... Description 1 Description The ST7DALIF2 device is a member of the ST7 microcontroller family designed for DALI applications running from 2.4 to 5.5 V. Different package options offer I/O pins. All devices are based on a common industry-standard 8-bit core, featuring an enhanced instruction set and are available with Flash or ROM program memory. The ST7 family architecture offers both power and flexibility to software developers, enabling the design of highly efficient and compact application code ...
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... RAM (stack) Data EEPROM Peripherals Operating supply CPU frequency Operating temperature Packages ST7DALIF2 8 Kbytes 384 (128) bytes 256 bytes Lite Timer with Watchdog, Autoreload Timer with 32 MHz input clock, SPI, 10-bit ADC with Op-Amp, DALI 2. MHz (with external OSC MHz and internal 1 MHz RC 1% PLLx8/4 MHz) -40° ...
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... OSC Internal 1MHz to CLOCK 16MHz LVD POWER SUPPLY CONTROL 8-BIT CORE ALU PROGRAM MEMORY (8K Bytes) RAM (384 Bytes) ST7DALIF2 12-Bit Auto-Reload TIMER 2 8-Bit LITE TIMER 2 PA7:0 PORT A (8 bits) PB6:0 PORT B (7 bits) ADC + OpAmp SPI DATA EEPROM ( 256 Bytes) WATCHDOG ...
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... ST7DALIF2 4 Pin description Figure 2. 20-pin SO package pinout CLKIN/AIN4/PB4 DALIIN/AIN6/PB6 RESET 3 SS/AIN0/PB0 4 ei0 SCK/AIN1/PB1 ei3 5 MISO/AIN2/PB2 6 MOSI/AIN3/PB3 7 8 ei2 ei1 AIN5/PB5 9 10 (HS) 20mA high sink capability eix Pin description OSC1/CLKIN 20 OSC2 19 PA0 (HS)/LTIC 18 PA1 (HS)/ATIC 17 PA2 (HS)/ATPWM0 16 PA3 (HS)/ATPWM1 ...
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... For details, refer to Section 20.2 on page 128 ADC Analog Input 2 or SPI Master In/ Slave Out Data ADC Analog Input 3 or SPI Master Out / Slave In Data ADC Analog Input 4 or External clock input ADC Analog Input 5 ADC Analog Input 6 or DALI Input ST7DALIF2 ...
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... ST7DALIF2 Table 2. Device pin description (continued) Level Pin Pin name no. 11 PA7/DALIOUT I PA6 /MCO/ 12 I/O C ICCCLK/BREAK PA5 /ATPWM3 ICCDATA 14 PA4/ATPWM2 I PA3/ATPWM1 I PA2/ATPWM0 I PA1/ATIC I PA0 /LTIC I OSC2 O 20 OSC1/CLKIN I Port / control Main function Input Output ...
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... Addressing RAM 017Fh 0180h 128 Bytes Stack 01FFh 8K FLASH PROGRAM MEMORY E000h 7 Kbytes SECTOR 1 FBFFh FC00h 1 Kbyte SECTOR 0 FFFFh ST7DALIF2 3) mapped in the upper part of the ST7 1000h RCCR0 RCCR1 1001h see Section 9.2 on page 32 FFDEh RCCR0 RCCR1 FFDFh see Section 9.2 on page 32 ...
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... ST7DALIF2 Table 3. Hardware register map Address Block 0000h 0001h Port A 0002h 0003h 0004h Port B 0005h 0006h 0007h 0008h 0009h LITE 000Ah TIMER 2 000Bh 000Ch 000Dh 000Eh 000Fh 0010h 0011h 0012h 0013h 0014h 0015h AUTO- 0016h RELOAD 0017h TIMER 2 0018h 0019h 001Ah ...
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... AWUCSR AWU Control/Status Register DMCR DM Control Register DMSR DM Status Register DMBK1H DM Breakpoint Register 1 High DMBK1L DM Breakpoint Register 1 Low DMBK2H DM Breakpoint Register 2 High DMBK2L DM Breakpoint Register 2 Low Reserved area (47 bytes) ST7DALIF2 Reset Remarks status 00h R/W xxh Read Only 0xh R/W 00h R/W 00h R/W FFh ...
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... ST7DALIF2 6 Flash program memory 6.1 Introduction The ST7 single voltage extended Flash (XFlash non-volatile memory that can be electrically erased and programmed either on a byte-by-byte basis bytes in parallel. The XFlash devices can be programmed off-board (plugged in a programming tool) or on- board using In-Circuit Programming or In-Application Programming ...
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... OSC1 and OSC2 grounded in this case. 5 With any programming tool, while the ICP option is disabled, the external clock has to be provided on PB4. Caution: During normal operation the ICCCLK pin must be pulled- up, internally or externally (external pull-up of 10k mandatory in noisy environment). This is to avoid entering ICC 20/171 ST7DALIF2 ...
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... ST7DALIF2 mode unexpectedly during a reset. In the application, even if the pin is configured as output, any reset will put it back in input pull-up. Figure 4. Typical ICC interface (See Note 3) APPLICATION POWER SUPPLY 6.5 Memory protection There are two different types of memory protection: Read Out Protection and Write/Erase Protection which can be applied individually ...
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... RASS Key: 1010 1110 (AEh) FCSR R/W R/W Table 4. Flash control/status register address and reset value Address (Hex) 002Fh FCSR reset value 22/171 R/W R/W Register label 0000 0000 (00h) Reset value OPT LAT R/W R/W R ST7DALIF2 0 PGM R ...
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... ST7DALIF2 7 Data EEPROM 7.1 Introduction The Electrically Erasable Programmable Read Only Memory can be used as a non volatile back-up for storing data. Using the EEPROM requires a basic access protocol described in this chapter. 7.2 Main features ■ Bytes programmed in the same cycle ■ EEPROM mono-voltage (charge pump) ■ ...
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... Data EEPROM programming flowchart IN EEPROM AREA 24/171 Figure 8. READ MODE E2LAT=0 E2PGM=0 READ BYTES (with the same 11 MSB of the address) CLEARED BY HARDWARE WRITE MODE E2LAT=1 E2PGM=0 WRITE BYTES IN EEPROM AREA START PROGRAMMING CYCLE E2LAT=1 E2PGM=1 (set by software E2LAT ST7DALIF2 ...
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... ST7DALIF2 Figure 7. Data EEPROM write operation ROW DEFINITION Byte 1 E2LAT bit E2PGM bit Note programming cycle is interrupted (by a reset action), the integrity of the data in memory is not guaranteed. 7.4 Power saving modes Wait mode The data EEPROM can enter Wait mode on execution of the WFI instruction of the microcontroller or when the microcontroller enters Active-Halt mode ...
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... Both Program Memory and data EEPROM are protected using the same option bit. Figure 8. Data EEPROM programming cycle INTERNAL PROGRAMMING VOLTAGE DATA LATCHES 26/171 READ OPERATION NOT POSSIBLE ERASE CYCLE WRITE OF t PROG ST7DALIF2 Section 22.1 on page READ OPERATION POSSIBLE WRITE CYCLE 161). LAT PGM ...
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... ST7DALIF2 7.7 Register description 7.8 EEPROM control/status register (EECSR) Read/Write Reset Value: 0000 0000 (00h Bits 7:2 = Reserved, forced by hardware to 0. Bit 1 = E2LAT Latch Access Transfer This bit is set by software cleared by hardware at the end of the programming cycle. It can only be cleared by software if the E2PGM bit is cleared. ...
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... Reset value = XXh 7 0 Reset value = XXh 7 0 Reset value = XXh PCL ST7DALIF2 Accumulator X index register Y index register Program counter Condition code register Stack pointer X = undefined value ...
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... ST7DALIF2 8.3.1 Accumulator (A) The Accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations and to manipulate data. 8.3.2 Index registers (X and Y) These 8-bit registers are used to create effective addresses or as temporary storage areas for data manipulation. (The Cross-Assembler generates a precede instruction (PRE) to indicate that the following instruction refers to the Y register ...
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... They can be also set/cleared by software with the RIM, SIM, IRET, HALT, WFI and PUSH/POP instructions. See Section 10: Interrupts on page 45 30/171 Function Function Table 8). Table 8). for more details. ST7DALIF2 Level Low High 1 ...
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... ST7DALIF2 8.3.5 Stack pointer register (SP R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W The Stack Pointer is a 16-bit register which is always pointing to the next free location in the stack then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see Since the stack is 128 bytes deep, the 9 most significant bits are forced by hardware ...
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... Whenever the microcontroller is reset, the RCCR returns to its default value (FFh), i.e. each time the device is reset, the calibration value must be loaded in the RCCR. Predefined calibration values are stored in EEPROM for 3 and shown in the following table. 32/171 ST7DALIF2 supply voltages at 25° ...
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... ST7DALIF2 Table 9. RC control registers RCCR RCCR0 RCCR1 Note: 1 Section 20: Electrical characteristics on page 127 and accuracy of the RC oscillator improve clock stability and frequency accuracy recommended to place a decoupling capacitor, typically 100nF, between the V device. 3 These two bytes are systematically programmed by ST, including on FASTROM devices. ...
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... LOCKED bit set 4/8 x input freq. t LOCK t STARTUP . STARTUP and Section 20.3.3: Internal RC oscillator and PLL on page for a description of the LOCKED bit in the SICSR register /32. OSC2 f CPU = OSC2 f /32) OSC2 t STAB reached after a stabilization time of PLL 0 0 MCO ST7DALIF2 131) 0 SMS ...
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... ST7DALIF2 9.4.2 RC control register (RCCR) Read / Write Reset Value: 1111 1111 (FFh) 7 CR70 CR60 Bits 7:0 = CR[7:0] RC Oscillator Frequency Adjustment Bits These bits must be written immediately after reset to adjust the RC oscillator frequency and to obtain an accuracy of 1%. The application can store the correct value for each voltage range in EEPROM and write it to this register at start-up ...
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... These oscillators are not stopped during the RESET phase to avoid losing time in the oscillator start-up phase. Internal RC oscillator In this mode, the tunable 1%RC oscillator is used as main clock source. The two oscillator pins have to be tied to ground. 36/171 ST7DALIF2 Section 22.1 on page ...
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... ST7DALIF2 Table 10. ST7 clock sources Crystal/Ceramic Resonators Internal RC Oscillator or Clock source External Clock External Clock on PB4 Supply, reset and clock management Hardware configuration ST7 OSC1 OSC2 EXTERNAL SOURCE ST7 OSC1 OSC2 C L1 LOAD CAPACITORS ST7 OSC1 OSC2 C L2 37/171 ...
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... If the PLL is enabled by option byte, it outputs the clock after an additional delay of t (see Figure 11). Figure 13. RESET sequence phases 38/171 for further details. Clock source RESET INTERNAL RESET Active Phase 256 or 4096 CLOCK CYCLES ST7DALIF2 Figure 14: Figure 13: CPU clock cycle delay 256 256 4096 STARTUP FETCH ...
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... ST7DALIF2 9.6.2 Asynchronous external RESET pin The RESET pin is both an input and an open-drain output with integrated R resistor. This pull-up has no fixed value but varies in accordance with the input voltage. It can be pulled low by external circuitry to reset the device. See Electrical Characteristic section for more details. ...
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... LVD RESET RUN ACTIVE PHASE t h(RSTL)in for further details. reference value. This means that it secures the power-up as well IT-(LVD) ST7DALIF2 EXTERNAL WATCHDOG RESET RESET RUN ACTIVE ACTIVE PHASE PHASE t w(RSTL)out WATCHDOG UNDERFLOW INTERNAL RESET (256 or 4096 T ...
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... ST7DALIF2 The LVD Reset circuitry generates a reset when V ● V when V IT+(LVD) ● V when V IT-(LVD) The LVD function is illustrated in The voltage threshold can be configured by option byte to be low, medium or high. Provided the minimum V the MCU can only be in two modes: ● ...
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... DD main supply DD 161). threshold (AVDF bit is set). STATUS FLAG AVD Interrupt Request 0 0 WDGRF LOCKED LVDRF AVDF AVDIE LOW VOLTAGE DETECTOR (LVD) AUXILIARY VOLTAGE DETECTOR (AVD) ). The V AVD IT-(AVD) reference value for rising IT+(AVD) Figure ST7DALIF2 IT-(AVD) 18. ...
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... ST7DALIF2 Figure 18. Using the AVD to monitor IT+(AVD) V IT-(AVD) V IT+(LVD) V IT-(LVD) AVDF bit AVD INTERRUPT REQUEST IF AVDIE bit = 1 LVD RESET 9.7.3 Low power modes Table 12. Effect of low power modes on SI Mode Wait Halt Interrupts The AVD interrupt event generates an interrupt if the corresponding Enable Control Bit (AVDIE) is set and the interrupt mask in the CC register is reset (RIM instruction) ...
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... The LVDRF flag is not cleared when another RESET type occurs (external or watchdog), the LVDRF flag remains set to keep trace of the original failure. In this case, a watchdog reset can be detected by software while an external reset can not. 44/171 0 WDGRF LOCKED RESET sources Figure 18 for additional details. ST7DALIF2 0 LVDRF AVDF AVDIE LVDRF WDGRF ...
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... ST7DALIF2 10 Interrupts The ST7 core may be interrupted by one of two different methods: maskable hardware interrupts as listed in the (TRAP). The Interrupt processing flowchart is shown in The maskable interrupts must be enabled by clearing the I bit in order to be serviced. However, disabled interrupts may be latched and processed when they are enabled (see ...
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... External interrupt control register (EICR) I BIT SET? Y FETCH NEXT INSTRUCTION N IRET? Y EXECUTE INSTRUCTION RESTORE PC FROM STACK THIS CLEARS I BIT BY DEFAULT ST7DALIF2 applies to the Section 12: I/O ports), a low level N N INTERRUPT PENDING? Y STACK PC SET I BIT LOAD PC FROM INTERRUPT VECTOR ...
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... ST7DALIF2 Table 15. Interrupt mapping Source N° Description block RESET Reset TRAP Software Interrupt 0 AWU Auto Wake Up Interrupt 1 ei0 External Interrupt 0 2 ei1 External Interrupt 1 3 ei2 External Interrupt 2 4 ei3 External Interrupt 3 5 LITE TIMER LITE TIMER RTC2 interrupt 6 DALI DALI ...
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... These bits are written by software. They select the Port B I/O pin used for the ei3 external interrupt according to the table below. 48/171 IS21 IS20 IS11 External interrupt sensitivity Falling edge & low level Rising edge only Falling edge only Rising and falling edge ei21 ei20 ei11 ST7DALIF2 0 IS10 IS01 IS00 Table 16. Table 16. Table 16. Table 16. Section 10.4: Interrupt ...
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... ST7DALIF2 Table 17. External interrupt I/O pin selection ei31 Reset state Bits 5:4 = ei2[1:0] ei2 pin selection These bits are written by software. They select the Port B I/O pin used for the ei2 external interrupt according to the table below. Table 18. External interrupt I/O pin selection ...
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... To adapt the internal clock frequency (f Slow mode is controlled by the SMS bit in the MCCSR register which enables or disables Slow mode. 50/171 Figure High RUN Slow Wait Slow Wait Active-halt AUTO WAKE UP FROM Halt Halt Low POWER CONSUMPTION ) to the available supply voltage. CPU ST7DALIF2 20): ). OSC2 ...
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... ST7DALIF2 In this mode, the oscillator frequency is divided by 32. The CPU and peripherals are clocked at this lower frequency. Note: Slow-Wait mode is activated when entering Wait mode while the device is already in Slow mode. Figure 21. Slow mode clock transition 11.3 Wait mode Wait mode places the MCU in a low power consumption mode by stopping the CPU. ...
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... INTERRUPT Y OSCILLATOR PERIPHERALS CPU I BIT 256 OR 4096 CPU CLOCK CYCLE DELAY OSCILLATOR PERIPHERALS CPU I BIT FETCH RESET VECTOR OR SERVICE INTERRUPT 47 RESET. When exiting Halt mode by means of a RESET ST7DALIF2 ON ON OFF 0 ON OFF Section 11.5 on page 54 Table 15: Figure 24) ...
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... ST7DALIF2 Figure 23. Halt mode timing overview Figure 24. Halt mode flowchart 1. WDGHALT is an option bit. See option byte section for more details. 2. Peripheral clocked with an external clock source can still be active. 3. Only some specific interrupts can exit the MCU from Halt mode (such as external interrupt). Refer to Table 15: Interrupt mapping 4 ...
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... All other peripherals are not clocked except those which get their clock supply from another clock generator (such as external or auxiliary oscillator). 54/171 ATCSRCK1 bit ATCSRCK0 bit 47 RESET. Figure 26). ST7DALIF2 Meaning Active-halt mode disabled Active-halt mode enabled Table 15: Figure 26). ...
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... ST7DALIF2 Note: As soon as Active-halt is enabled, executing a HALT instruction while the Watchdog is active does not generate a RESET. This means that the device cannot spend more than a defined delay in this power saving mode. Figure 25. Active-halt timing overview Figure 26. Active-halt mode flowchart Notes This delay occurs only if the MCU exits Active-halt mode by means of a RESET. ...
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... None of the peripherals are 56/171 AWU RC oscillator to Timer input capture f AWU_RC /64 AWUFH prescaler/1 .. 255 divider and then calculating the right prescaler value. AWU_RC to the input capture of the 12-bit Auto-Reload timer, allowing AWU_RC Section 11.4: Halt mode). ST7DALIF2 AWUFH interrupt (ei0 source) ). Its frequency is divided by AWU_RC ...
Page 57
... ST7DALIF2 clocked except those which get their clock supply from another clock generator (such as an external or auxiliary oscillator like the AWU oscillator). ● The compatibility of Watchdog operation with AWUFH mode is configured by the WDGHALT option bit in the option byte. Depending on this setting, the HALT instruction when executed while the Watchdog system is enabled, can generate a Watchdog RESET ...
Page 58
... AWU RC OSC MAIN OSC PERIPHERALS CPU I[1:0] BITS FETCH RESET VECTOR OR SERVICE INTERRUPT Table 15: Interrupt mapping on page WATCHDOG DISABLE ON OFF 2) OFF OFF 10 RESET Y OFF ON OFF CYCLE DELAY OFF for more details. (see STARTUP AWU 0 AWUM F ST7DALIF2 0 AWUEN ...
Page 59
... ST7DALIF2 Bit 2 = AWUF Auto Wake Up Flag This bit is set by hardware when the AWU module generates an interrupt and cleared by software on reading AWUCSR. Writing to this bit does not change its value AWU interrupt occurred 1: AWU interrupt occurred Bit 1= AWUM Auto Wake Up Measurement This bit enables the AWU RC oscillator and connects its output to the input capture of the 12-bit Auto-Reload timer ...
Page 60
... HALT instruction, or the AWUPR remains unchanged. Table 23. AWU register map and reset values Address Register 7 (Hex.) label AWUPR AWUPR7 0049h Reset Value 1 AWUCSR 004Ah 0 Reset Value 60/171 AWUPR6 AWUPR5 AWUPR4 ST7DALIF2 AWUPR3 AWUPR2 AWUPR1 AWUF AWUM 0 AWUPR0 1 AWUEN ...
Page 61
... ST7DALIF2 12 I/O ports 12.1 Introduction The I/O ports allow data transfer. An I/O port can contain pins. Each pin can be programmed independently either as a digital input or digital output. In addition, specific pins may have several other functions. These functions can include external interrupt, alternate signal input/output for on-chip peripherals or analog input. ...
Page 62
... I/O through the latch. Reading the DR bits returns the previously stored value bit is available, different output modes can be selected by software: push-pull or open-drain. Refer to I/O Port Implementation section for configuration. Table 24. DR value and output pin status 62/171 Push-pull ST7DALIF2 Open-drain V OL Floating ...
Page 63
... ST7DALIF2 12.2.3 Alternate functions Many ST7s I/Os have one or more alternate functions. These may include output signals from, or input signals to, on-chip peripherals. The describes which peripheral signals can be input/output to which ports. A signal coming from an on-chip peripheral can be output this, enable the on-chip peripheral as an output (enable bit in the peripheral’ ...
Page 64
... The diode to VDD is not implemented in the true open drain pads. A local protection between the pad and VOL is implemented to protect the device against positive stress. Legend Off - implemented not activated On - implemented and activated 64/171 Pull-up Off On Off NI not implemented ST7DALIF2 Diodes P-buffer Off Off (1) NI ...
Page 65
... ST7DALIF2 Table 26. I/O configurations PAD PAD PAD 1. When the I/O port is in input configuration and the associated alternate function is enabled as an output, reading the DR register will read the alternate function output status. 2. When the I/O port is in output configuration and the associated alternate function is enabled as an input, the alternate function reads the pin status given by the DR register content ...
Page 66
... No effect on I/O ports. External interrupts cause the device to exit from Wait mode. No effect on I/O ports. External interrupts cause the device to exit from Halt mode. Event flag - 10 11 OUTPUT push-pull XX = DDR, OR Section 20. Description Enable Exit control from bit Wait DDRx Yes ORx ST7DALIF2 Figure 31. Exit from Halt Yes ...
Page 67
... ST7DALIF2 12.7 Device-specific I/O port configuration The I/O port register configurations are summarized as follows. Table 29. Ports PA7:0, PB6:0 with interrupt capability not selected in EISR register floating input pull-up input open drain output push-pull output Table 30. Ports PA7:0, PB6:0 with interrupt capability selected in EISR register ...
Page 68
... I/O port register map and reset values (continued) Address Register label (Hex.) PBDR 0003h Reset Value PBDDR 0004h Reset Value PBOR 0005h Reset Value 68/171 MSB MSB MSB ST7DALIF2 LSB LSB LSB ...
Page 69
... ST7DALIF2 13 Watchdog timer (WDG) 13.1 Introduction The Watchdog timer is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to abandon its normal sequence. The Watchdog circuit generates an MCU reset on expiry of a programmed time period, unless the program refreshes the counter’s contents before the T6 bit becomes cleared ...
Page 70
... WDG reset immediately after waking up the microcontroller. The same behavior occurs in Active-halt mode. 13.5 Interrupts None. 70/171 34 MHz.) CPU min [ms] 1 127 Table 34 is due to the unknown status of the prescaler when Section 22.1 on page ST7DALIF2 max [ms] 2 128 161. ...
Page 71
... ST7DALIF2 13.6 Register description 13.6.1 Control register (CR) Read/Write Reset Value: 0111 1111 (7Fh) 7 WDGA Bit 7 = WDGA Activation bit. This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the watchdog can generate a reset. 0: Watchdog disabled 1: Watchdog enabled Note: This bit is not used if the hardware watchdog option is enabled by option byte. ...
Page 72
... Generation of four independent PWMx signals ■ Frequency 2 kHz-4 MHz (@ 8 MHz f – Programmable duty-cycles – Polarity control – Programmable output modes – Maskable Compare interrupt ■ Input Capture – 12-bit input capture register (ATICR) – Triggered by rising and falling edges – Maskable IC interrupt 72/171 ) CPU ST7DALIF2 ...
Page 73
... ST7DALIF2 Figure 33. Block diagram ATIC ATCSR f LTIMER (1 ms timebase @ 8MHz) f CPU 32 MHz DCR0H Preload 12-BIT DUTY CYCLE VALUE (shadow) 4 PWM Channels 14.3 Functional description 14.3.1 PWM mode This mode allows up to four Pulse Width Modulated signals to be generated on the PWMx output pins. The PWMx output signals can be enabled or disabled using the OEx bits in the PWMCR register ...
Page 74
... Figure 35. PWM function 4095 DUTY CYCLE REGISTER (DCRx) AUTO-RELOAD REGISTER (ATR) 000 WITH OE=1 AND OPx=0 WITH OE=1 AND OPx=1 74/171 34. inverter PWMx PWMxCSR Register OPx DFF TRAN TRANCR Register counter overflow ST7DALIF2 PWMx PIN t ...
Page 75
... ST7DALIF2 Figure 36. PWM signal from 0% to 100% duty cycle f COUNTER COUNTER DCRx=000h DCRx=FFDh DCRx=FFEh DCRx=000h 14.3.2 Output compare mode To use this function, load a 12-bit value in the DCRxH and DCRxL registers. When the 12-bit upcounter (CNTR) reaches the value stored in the DCRxH and DCRxL registers, the CMPF bit in the PWMxCSR register is set and an interrupt request is generated if the CMPIE bit is set ...
Page 76
... PWM1 PWM2 PWM3 (Inverters) 02h 03h 04h 05h INTERRUPT xxh PWM0 1 PWM1 PWM2 PWM3 0 When BA is set: PWM counter -> Reset value ARR & DCRx -> Reset value PWM Mode -> Reset value 06h 07h 08h 09h 0Ah ATICR READ 09h 04h ST7DALIF2 INTERRUPT t ...
Page 77
... ST7DALIF2 14.4 Low power modes Table 36. Effect of low power modes on AT2 timer Mode Slow Wait Active-halt Halt 14.5 Interrupts Table 37. AT2 timer interrupt control bits Interrupt event Overflow event IC event CMP event 1. The CMP and IC events are connected to the same interrupt vector. The OVF event is mapped on a separate vector (see ATCSR register and the interrupt mask in the CC register is reset (RIM instruction) ...
Page 78
... To obtain the 12-bit value, 78/171 Counter clock selection OFF timebase @ 8 MHz) LTIMER f CPU (2) 32 MHz 0 0 CNTR5 CNTR4 CK1 0 ( CNTR CNTR CNTR9 11 10 CNTR3 CNTR2 CNTR1 ST7DALIF2 CK0 CNTR8 0 CNTR0 ...
Page 79
... ST7DALIF2 software should read the counter value in two consecutive read operations. The CNTRH register can be incremented between the two reads, and in order to be accurate when the software should take this into account when CNTRL and CNTRH are read. TIMER CPU ...
Page 80
... These bits are read/write by software and cleared by hardware after a reset. They are used to force the four PWMx output signals into a stable state when the Break function is active. 14.6.9 PWMx duty cycle register high (DCRxH) Read / Write Reset Value: 0000 0000 (00h 80/171 BA BPEN PWM3 0 0 DCR11 ST7DALIF2 0 PWM2 PWM1 PWM0 8 DCR10 DCR9 DCR8 ...
Page 81
... ST7DALIF2 14.6.10 PWMx duty cycle register low (DCRxL) Read / Write Reset Value: 0000 0000 (00h) 7 DCR7 DCR6 Bits 15:12 = Reserved. Bits 11:0 = DCR[11:0] PWMx Duty Cycle Value This 12-bit value is written by software. It defines the duty cycle of the corresponding PWM output signal (see In PWM mode (OEx=1 in the PWMCR register) the DCR[11:0] bits define the duty cycle of the PWMx output signal (see be compared with the 12-bit upcounter value ...
Page 82
... ATR7 ATR6 ATR5 ATR4 OE3 OE2 ST7DALIF2 TRAN CK0 OVF OVFIE CMPIE CNTR1 CNTR1 CNTR9 CNTR8 CNTR3 CNTR2 CNTR1 CNTR0 0 ...
Page 83
... ST7DALIF2 Table 39. Register map and reset values (continued) Address Register label (Hex.) PWM3CSR 16 Reset Value DCR0H 17 Reset Value DCR0L 18 Reset Value DCR1H 19 Reset Value DCR1L 1A Reset Value DCR2H 1B Reset Value DCR2L 1C Reset Value DCR3H 1D Reset Value DCR3L 1E Reset Value ATICRH 1F Reset ...
Page 84
... LTICR LTIC INPUT CAPTURE REGISTER 84/171 OSC2 LTCSR2 Timebase f LTIMER 8MHz f ) OSC2 8 8-bit LTCSR1 ICIE ICF TB TB1IE TB1F ST7DALIF2 ) OSC2 ) LTTB2 Interrupt request 0 0 TB2IE TB2F f LTIMER To 12-bit AT TImer LTTB1 INTERRUPT REQUEST LTIC INTERRUPT REQUEST ...
Page 85
... ST7DALIF2 15.3 Functional description 15.3.1 Timebase counter 1 The 8-bit value of Counter 1 cannot be read or written by software. After an MCU reset, it starts incrementing from frequency of f counter rolls over from F9h to 00h counter overflow events is 1 ms. This period can be doubled by setting the TB bit in the LTCSR1 register ...
Page 86
... No effect on Lite timer No effect on Lite timer Lite timer stops counting Enable Exit Event control from flag bit Wait TB1F TB1IE TB2F TB2IE ICF ICIE ST7DALIF2 /32) OSC2 Exit Exit from from Active- Halt halt Yes Yes No Yes No No Yes ...
Page 87
... ST7DALIF2 Bit 0 = TB2F Timebase 2 Interrupt Flag. This bit is set by hardware and cleared by software reading the LTCSR register. Writing to this bit has no effect Counter 2 overflow 1: A Counter 2 overflow has occurred 15.6.2 Lite timer autoreload register (LTARR) Read / Write Reset Value: 0000 0000 (00h) ...
Page 88
... MHz) OSC ICR5 ICR4 ICR3 AR7 AR6 AR5 AR4 CNT7 CNT6 CNT5 CNT4 ST7DALIF2 0 ICR2 ICR1 ICR0 TB2IE TB2F AR3 AR2 AR1 AR0 CNT3 CNT2 CNT1 CNT0 0 0 ...
Page 89
... ST7DALIF2 Table 42. Lite timer register map and reset values (continued) Address Register label (Hex.) LTCSR1 0B Reset Value LTICR 0C Reset Value ICIE ICF TB TB1IE ICR7 ICR6 ICR5 ICR4 Lite timer 2 (LT2 TB1F ICR3 ...
Page 90
... Register f CPU 8 8-bit DCMFD Register 8 8-bit DCMBD Register ITE ITF EF RTF CK3 CK2 DCM Interrupt Request DCME RTA ST7DALIF2 DALIOUT f DALI 4-bit Pre-shift DALIIN Register Edge Detector Arbitration & Error Detection DCMCSR CK1 CK0 Register DCMCR RTS FTS Register ...
Page 91
... ST7DALIF2 16.3 DALI standard protocol The DALI protocol uses the bi-phase Manchester asynchronous serial data format. All the bits of the frame are bi-phase encoded except the two stop bits. ■ The transmission rate is about 1.2 kHz. The bi-phase bit period is 833.33 us ±10%. ■ ...
Page 92
... When the "backward frame" has been transmitted, the DCM will send an interrupt signal by setting the ITF bit in the DCMCSR register. 92/171 = f /[(N+1)*16] CPU is 1.2 kHz the integer value of the DCMCLK register. DALI is 8 MHz, the integer value of the DCMCLK register is CPU ST7DALIF2 = DATA DALI ...
Page 93
... ST7DALIF2 If the software asks the DCM to receive a "forward frame", the software must switch the DCM to Receive state by clearing the RTS bit and setting the RTA bit in the DCMCR register during the interrupt routine. If the ITF interrupt flag is set in the DCMCSR register, the software must set the RTA bit in the DCMCR register to allow the DCM to perform the next DALI signal reception or transmission ...
Page 94
... The 4-bit pre-shifter is used to detect any errors in the received frame. When a change of phase is detected (edge trigger), the 4-bit sample clock counter (integer range 0 to15) is cleared. 94/171 No effect on DCM DCM registers are frozen No effect on DCM Enable Event control flag ITF Description Exit from bit Wait ITE Yes ST7DALIF2 Exit from Halt No ...
Page 95
... ST7DALIF2 Figure 43. DALI signal sampling DALI Signal 4-bit sample clock counter Phase Detector Shifter Clock 4-bit Pre-shifter x 16-bit Shifter xxxx Edge Trigger In the example shown in each edge trigger (DALI signal change of phase). At the same time the value of the 4-bit sample clock counter is reset ...
Page 96
... CPU CPU m 0000 0001 1111 0000 0000 CPU N = 207 (DCMCLK µs (208 x 125ns 125ns CPU CK5 CK4 CK3 DATA FA5 FA4 FA3 ST7DALIF2 t CPU 0000 xxxx xxxx 1111 0 CK2 CK1 CK0 = f /[(N+1)*16] where N is the CPU 0 FA2 FA1 FA0 ...
Page 97
... ST7DALIF2 Bits 7:0 = DCMFA[7:0] Forward Address. These bits are read by software and set/cleared by hardware. These 8 bits are used to store the "forward frame" address byte. 16.11.3 DCM forward data register (DCMFD) Read only Reset Value: 0000 0000 (00h) 7 FD7 FD6 Bits 7:0 = DCMFD[7:0] Forward Data. ...
Page 98
... This bit is set when either the DALI data format received is wrong or an interface failure is detected data format error during reception 1: Data format error during reception Bit 4 = RTF Receive/Transmit Flag. (Read only) This bit is set/reset by hardware and read by software. 98/171 EF RTF CK3 ST7DALIF2 0 CK2 CK1 CK0 ...
Page 99
... ST7DALIF2 0: The DCM is in Transmit state 1: The DCM is in Receive state Bits 3:0 = DCMCSR[3:0] Clock counter value. (Read only) These bits are set/cleared by hardware and read by software. The value of the 4-bit sample clock counter (integer range 0 to 15). The clock counter value is loaded in the DCMCSR register when a DALI change of phase signal is detected (edge trigger) ...
Page 100
... SCK: Serial Clock out by SPI masters and input by SPI slaves – SS: Slave select: This input signal acts as a ‘chip select’ to let the SPI master communicate with slaves individually and to avoid contention on the data lines. Slave SS inputs can be driven by standard I/O ports on the master device. 100/171 /4 max.) CPU ST7DALIF2 ...
Page 101
... ST7DALIF2 Figure 45. Serial peripheral interface block diagram MOSI MISO SOD bit SCK SS 17.4 Functional description A basic example of interconnections between a single master and a single slave is illustrated in Figure The MOSI pins are connected together and the MISO pins are connected together. In this way data is transferred serially between master and slave (most significant bit first). ...
Page 102
... Figure 47. Generic SS timing diagram MOSI/MISO Master SS Slave SS (if CPHA=0) Slave SS (if CPHA=1) 102/171 LSBit MISO MISO MOSI MOSI SCK SCK SS SS +5V Figure 48) 106). Byte 1 Byte 2 ST7DALIF2 SLAVE MSBit LSBit 8-BIT SHIFT REGISTER Not used managed by software Figure 47 made free for SS Write Byte 3 ...
Page 103
... ST7DALIF2 Figure 48. Hardware/software slave select management 17.4.2 Master mode operation In master mode, the serial clock is output on the SCK pin. The clock frequency, polarity and phase are configured by software (refer to the description of the SPICSR register). Note: The idle state of SCK must correspond to the polarity selected in the SPICSR register (by pulling up SCK if CPOL=1 or pulling down SCK if CPOL=0) ...
Page 104
... The idle state of SCK must correspond to the polarity selected in the SPICSR register (by pulling up SCK if CPOL=1 or pulling down SCK if CPOL=0). The combination of the CPOL clock polarity and CPHA (clock phase) bits selects the data capture clock edge 104/171 49). Section 17.4.1 ST7DALIF2 and Figure 47. If CPHA=1 SS Overrun condition ...
Page 105
... ST7DALIF2 Figure 49, shows an SPI transfer with the four combinations of the CPHA and CPOL bits. The diagram may be interpreted as a master or slave timing diagram where the SCK pin, the MISO pin, the MOSI pin are directly connected between the master and the slave device. ...
Page 106
... The WCOL bit in the SPICSR register is set if a write collision occurs. No SPI interrupt is generated when the WCOL bit is set (the WCOL bit is a status flag only). Clearing the WCOL bit is done through a software sequence (see 106/171 ST7DALIF2 Section 17.4.1: Slave Figure 50). ...
Page 107
... ST7DALIF2 Figure 50. Clearing the WCOL bit (write collision flag) software sequence Clearing sequence after SPIF = 1 (end of a data byte transfer) Read SPICSR 1st Step 2nd Step Read SPIDR Clearing sequence before SPIF = 1 (during a data byte transfer) 1st Step 2nd Step Note: Writing to the SPIDR register instead of reading it does not reset the WCOL bit ...
Page 108
... Halt mode only if the Slave Select signal (external SS Device Section SS SS SCK SCK Slave Slave Device Device MOSI MISO MOSI MISO Description from Halt mode through a SPIF Device enters Halt mode Slave Device 17.4.1), make sure the master drives a low ST7DALIF2 ...
Page 109
... ST7DALIF2 17.6 Interrupts Table 47. Interrupt control bits Interrupt Event SPI End of Transfer Event Master Mode Fault Event Overrun Error Note: The SPI interrupt events are connected to the same interrupt vector (see Interrupts chapter). They generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask in the CC register is reset (RIM instruction) ...
Page 110
... This bit is set by hardware when a transfer has been completed. An interrupt is generated if 110/171 SPR2 f /4 CPU f /8 CPU f /16 CPU f /32 CPU f /64 CPU /128 CPU OVR MODF 105). SPR1 SOD SSM ST7DALIF2 SPR0 SSI ...
Page 111
... ST7DALIF2 SPIE=1 in the SPICR register cleared by a software sequence (an access to the SPICSR register followed by a write or a read to the SPIDR register). 0: Data transfer is in progress or the flag has been cleared. 1: Data transfer between the Note: While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR register is read ...
Page 112
... Value SPICSR 0033h Reset Value 112/171 Figure 45 MSB SPIE SPE SPR2 MSTR SPIF WCOL OVR MODF ST7DALIF2 CPOL CPHA SPR1 SOD SSM LSB x SPR0 x SSI ...
Page 113
... ST7DALIF2 18 10-bit A/D converter (ADC) 18.1 Introduction The on-chip Analog to Digital Converter (ADC) peripheral is a 10-bit, successive approximation converter with internal sample and hold circuitry. This peripheral has multiplexed analog input channels (refer to device pin out description) that allow the peripheral to convert the analog voltage levels from different sources. ...
Page 114
... ADC can convert voltages in the range 0V to 430mV with ) is greater than V (high-level voltage reference) then the AIN DDA ) is lower than V (low-level voltage reference) then the AIN SSA f ADC ADCCSR CH0 ANALOG TO DIGITAL CONVERTER C ADC AMP AMP SLOW D1 D0 CAL SEL /8. DD ST7DALIF2 ...
Page 115
... ST7DALIF2 R is the maximum recommended impedance for an analog input signal. If the impedance AIN is too high, this will result in a loss of accuracy due to leakage and sampling not being completed in the alloted time. 18.3.4 A/D conversion The analog input ports must be configured as input, no pull-up, no interrupt. Refer to Section 12: I/O ports on page ability of the port to be read as a logic input ...
Page 116
... A/D Converter disabled. After wakeup from Halt mode, the A/D Converter requires a stabilization time t (see Electrical Characteristics) before accurate conversions can be STAB performed. ADON 0 (1) Channel pin AIN0 AIN1 AIN2 Description CH3 CH2 CH1 CH2 CH1 ST7DALIF2 0 CH0 CH0 ...
Page 117
... ST7DALIF2 Table 51. Channel selection bits (continued) 1. The number of channels is device dependent. Refer to 18.7.2 Data register high (ADCDRH) Read Only Reset Value: xxxx xxxx (xxh Bits 7:0 = D[9:2] MSB of Analog Converted Value 18.7.3 AMP control/data register low (ADCDRL) Read/Write Reset Value: 0000 00xx (0xh Bits 7:5 = Reserved ...
Page 118
... Reset Value 118/171 be less than or equal to 2 MHz. ADC EOC SPEED ADON AMPC ST7DALIF2 CH2 CH1 CH0 AMPSE SLOW ...
Page 119
... ST7DALIF2 19 Instruction set 19.1 CPU addressing modes The CPU features 17 different addressing modes which can be classified in 7 main groups (see Table 54). : Table 54. Addressing mode groups Addressing mode Inherent Immediate Direct Indexed Indirect Relative Bit operation The CPU Instruction Set is designed to minimize the number of bytes required per ...
Page 120
... Set Interrupt Mask (level 3) Reset Interrupt Mask (level 0) Set Carry Flag Reset Carry Flag Reset Stack Pointer Load Clear Push/Pop to/from the stack Increment/Decrement Test Negative or Zero Complement Byte Multiplication Shift and Rotate operations Swap nibbles ST7DALIF2 + 1 00..FF byte + 00..FF byte + 00..FF byte + 3 Function ...
Page 121
... ST7DALIF2 . Table 57. Immediate instructions Instruction LD CP BCP AND, OR, XOR ADC, ADD, SUB, SBC 19.1.3 Direct In Direct instructions, the operands are referenced by their memory address. The direct addressing mode consists of two submodes: Direct (short) The address is a byte, thus requiring only one byte after the opcode, but only allows addressing space ...
Page 122
... Clear INC, DEC Increment/Decrement TNZ Test Negative or Zero CPL, NEG Complement BSET, BRES Bit operations BTJT, BTJF Bit Test and Jump operations SLL, SRL, SRA, RLC, RRC Shift and Rotate operations SWAP Swap nibbles CALL, JP Call or Jump sub-routine ST7DALIF2 Function ...
Page 123
... ST7DALIF2 19.1.7 Relative mode (direct, indirect) This addressing mode is used to modify the PC register value, by adding an 8-bit signed offset to it. . Table 59. Relative direct and indirect instructions and functions Available relative direct/indirect instructions JRxx CALLR The relative addressing mode consists of two submodes: Relative (direct) The offset follows the opcode ...
Page 124
... If a code to be executed does not correspond to any opcode or prebyte value, a reset is generated. This, combined with the Watchdog, allows the detection and recovery from an unexpected fault or interference. Note: A valid prebyte associated with a valid opcode forming an unauthorized combination does not generate a reset. 124/171 ST7DALIF2 ...
Page 125
... ST7DALIF2 Table 61. Instruction set overview Mnemo Description ADC Add with Carry ADD Addition AND Logical And BCP Bit compare A, memory BRES Bit reset BSET Bit set BTJF Jump if bit is false (0) BTJT Jump if bit is true (1) CALL Call sub-routine CALLR Call sub-routine relative ...
Page 126
... I1 (level 3) C <= A <= 0 reg <= A <= 0 reg => A => C reg => A => C reg A7-A4 <=> A3-A0 reg, M tnz lbl1 S/W interrupt XOR M A ST7DALIF2 Src reg ...
Page 127
... ST7DALIF2 20 Electrical characteristics 20.1 Parameter conditions Unless otherwise specified, all voltages are referred to V 20.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at T selected temperature range) ...
Page 128
... Input voltage on any pin Electrostatic discharge voltage (Human Body Model) ) lines must always be connected to the external supply could damage the device if an unexpected change of the I according to their reset configuration ST7DALIF2 Maximum value Unit see Section 20.7 ...
Page 129
... ST7DALIF2 Table 63. Current characteristics Symbol I VDD I VSS I IO (1) & (2) I INJ(PIN) ΣI 2) INJ(PIN must never be exceeded. This is implicitly insured if V INJ(PIN) respected, the injection current must be limited externally to the I while a negative injection is induced by V corresponding V maximum must always be respected IN 2. ...
Page 130
... Parameter MHz. max., CPU MHz. max. CPU 3.3V≤ 2.4V≤V DD Maximum operating frequency versus V 2.0 2.4 2.7 3.3 3.5 4.0 Conditions Min 2.4 3.3 ≤5. <3. supply voltage DD FUNCTIONALITY GUARANTEED IN THIS AREA (UNLESS OTHERWISE STATED IN THE TABLES OF PARAMETRIC DATA) SUPPLY VOLTAGE [V] 5.5 4.5 5.0 ST7DALIF2 Max Unit 5.5 V 5.5 MHz ...
Page 131
... ST7DALIF2 20.3.1 Operating conditions with low voltage detector (LVD -40 to 85°C, unless otherwise specified A Table 66. Power on/power down operating conditions Symbol Reset release threshold V IT+ (LVD) (V rise) DD Reset generation threshold V IT- (LVD) (V fall) DD LVD voltage threshold V hys hysteresis Vt V rise time rate ...
Page 132
... A DD Min Typ =25° C, 760 =5 V 1000 (3) -2 (3) 970 ( (5) =4.5 to 5.5 V 0.1 ( 0.1 DD (6) 125 (6) 1 (3) 600 34. accuracy. PLL ST7DALIF2 Unit V PLL input clock (f ) PLL cycles = 4.5 to Max Unit kHz + ( μA μs (2) 10 MHz µs % μA ...
Page 133
... ST7DALIF2 Table 70. RC oscillator and PLL characteristics (tested for T 3.3 V Symbol Parameter Internal RC oscillator ( frequency Accuracy of Internal RC oscillator when ACC RC calibrated with (3)(2) RCCR=RCCR1 RC oscillator current I DD(RC) consumption t RC oscillator setup time T su(RC PLL input clock PLL (4) t PLL Lock time LOCK ...
Page 134
... Figure 59. RC Osc Freq vs V =5V DD 1.80 1.60 1. 1.20 1.00 0.80 0.60 0.40 0.20 85 125 0.00 /f versus time CPU CPU CPU t w(JIT) DD (Calibrated with RCCR0: 5V@ 25°C) 2.5 3 3.5 4 4.5 5 5.5 Vdd (V) and RCCR DD Value 2.4 2.7 3 3.3 3.75 4 4.5 5 5.5 Vdd ( w(JIT) ST7DALIF2 -45° 0° 25° 90° 105° 130° 6 rccr=00h rccr=64h rccr=80h rccr=C0h rccr=FFh 6 ...
Page 135
... ST7DALIF2 Figure 61. PLLx4 Output vs CLKIN frequency ( /2*PLL4) OSC CLKIN 7.00 6.00 5.00 4.00 3.00 2.00 1.00 1 1.5 2 External Input Clock Frequency (MHz -40 to 85°C, unless otherwise specified A Table 71. 32 MHz PLL Symbol PLL32 f INPUT 1. 32 MHz is guaranteed within this voltage range. 20.4 Supply current characteristics The following current consumption specified for the ST7 functional operating modes over temperature range does not take into account the clock source current consumption ...
Page 136
... CPU (2) 3.7 (3) 1.6 (4) 1.6 ≤+85° (no load), all peripherals in reset state; clock SS max. CPU (no load). Data tested in production Slow vs 250Khz 125Khz 62.5Hz 2 2.5 3 3.5 4 4.5 5 Vdd (V) ST7DALIF2 Max Unit 2.5 2 μA 30 (no load), all max. DD CPU 5.5 6 ...
Page 137
... ST7DALIF2 Figure 65. Typical I in Wait vs 4.5 4.0 8Mhz 3.5 4Mhz 3.0 2.5 1MHz 2.0 1.5 1.0 0.5 0.0 2.0 2.5 3.0 3.5 4.0 Vdd (V) Figure 67. Typical I in AWUFH mode =25°C A 0.035 fawu_rc ~125 KHz 0.030 0.025 0.020 0.015 0.010 0.005 0.000 2.0 2.5 3.0 3.5 4.0 Vdd(V) On-chip peripherals Table 73. Symbol I 12-bit Auto-Reload Timer supply current DD(AT) I SPI supply current ...
Page 138
... Min Typ Max 250 375 1500 10 22 1.25 2.75 is the number of t c(INST) CPU Min Typ Max Unit 50 125 250 kHz 50 Min Typ Max 2 16 See table below Section 9: Supply, reset and ST7DALIF2 Unit t CPU ns t CPU μs cycles µs Unit MHz pF ...
Page 139
... ST7DALIF2 Table 77. Typical ceramic resonators f CrOSC Supplier [MHz Resonator characteristics given by the ceramic resonator manufacturer. For more information on these resonators, please consult www.murata.com 2. () means load capacitor built in resonator 3. SMD = -R0: Plastic tape package ( Figure 69. Typical application with a crystal or ceramic resonator ...
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... Read / Write / Erase modes MHz, V CPU 5 Read/No Write Mode Power down mode / Halt decreases. A Parameter Conditions =−40 to +85° (1) (2) T =+55°C A =+25° decreases. A ST7DALIF2 Min Typ Max 2.4 5 0.24 0.48 (3) 20 10K (4) (5) 2 100 0 0.1 Min Typ Max 2.4 5.5 5 ...
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... ST7DALIF2 20.7 EMC characteristics Susceptibility tests are performed on a sample basis during product characterization. 20.7.1 Functional EMS (electromagnetic susceptibility) Based on a simple running application on the product (toggling 2 LEDs through I/O ports), the product is stressed by two electromagnetic events until a failure occurs (indicated by the LEDs). ■ ...
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... MHz to 130 MHz SO20 package, conforming to SAE J 130 MHz to 1 GHz 1752/3 SAE EMI Level Conditions =+25° conforming to AEC-Q100- 002 Parameter =+25° C conforming to JESD ST7DALIF2 Max vs OSC2 CPU Monitored 8/4 16/8 MHz MHz 3.5 4 ...
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... ST7DALIF2 20.8 I/O port pin characteristics 20.8.1 General characteristics Subject to general operating conditions for V Table 85. General characteristics Symbol Parameter V Input low level voltage IL V Input high level voltage IH Schmitt trigger voltage V (1) hys hysteresis I Input leakage current L Static current consumption I induced by each floating input ...
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... Electrical characteristics Figure 71. Typical I 144/171 vs. V with Ta=1 40°C 80 Ta=9 5°C 70 Ta=2 5°C Ta=-45 ° 2.5 3 3.5 4 4.5 Vdd(V) ST7DALIF2 5 5.5 6 ...
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... ST7DALIF2 Table 86. Output driving current Symbol Parameter Output low level voltage for a standard I/O pin when 8 pins are sunk at same time (see Figure 75) ( Output low level voltage for a high sink I/O pin when 4 pins are sunk at same time (see Figure 77) ...
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... V =2.7 V (standard 0. lio (mA (standard 0. lio (mA (high-sink lio ( ST7DALIF2 -45°C 0°C 25°C 90°C 130°C -45°C 0°C 25°C 90°C 130°C -45 0°C 25°C 90°C 130°C 40 ...
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... ST7DALIF2 Figure 78. Typical 1.20 1.00 0.80 0.60 0.40 0.20 0. lio (mA) Figure 80. Typical 1.20 1.00 0.80 0.60 0.40 0.20 0.00 -0.01 -1 lio(mA) Figure 82. Typical 2.50 2.00 1.50 1.00 0.50 0.00 -0. lio (mA (high-sink) Figure 79. Typical V DD 1.60 1.40 1.20 -45 1.00 0°C 0.80 25°C 90°C 0.60 130°C 0.40 0.20 0. =2.7 V Figure 81. Typical V DD 1.60 1.40 1.20 -45°C 1.00 0°C 0.80 25°C 90°C 0.60 130°C ...
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... VDD ( 1.10 1.00 0.90 -45°C 0.80 0°C 25°C 0.70 90°C 130°C 0.60 0.50 0.40 5 VDD ST7DALIF2 -45 0°C 25°C 90°C 130°C 2.4 2.7 3.3 5 VDD (V) -45 0°C 25°C 90°C 130°C 2 VDD (V) -45°C 0°C 25°C 90°C 130°C 2.4 2 VDD (V) ...
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... ST7DALIF2 20.9 Control pin characteristics T = -40°C to 85°C, unless otherwise specified A Table 87. Asynchronous RESET pin characteristics Symbol Parameter V Input low level voltage IL V Input high level voltage IH Schmitt trigger voltage V (1) hys hysteresis V Output low level voltage OL R Pull-up equivalent resistor ...
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... Otherwise: Replace 10 nF pull-down on the RESET pin with a 5 µ µF capacitor. Figure 87. RESET pin protection when LVD is enabled. Required EXTERNAL RESET 0.01μF 150/171 max. level specified in IL Section 20.2 on page 128 Optional R ON Filter 1MΩ ST7DALIF2 Section 20.8. Otherwise ST72XXX INTERNAL RESET WATCHDOG PULSE ILLEGAL OPCODE GENERATOR LVD RESET ...
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... ST7DALIF2 RESET pin protection when LVD is disabled When the LVD is disabled recommended to protect the RESET pin as shown in Figure 88 and follow these guidelines: 1. The reset network protects the device against parasitic resets. 2. The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad ...
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... MSB OUT BIT6 OUT t t su(SI) h(SI) MSB IN Min Max ( +150 CPU 120 100 90 100 100 100 100 0 120 240 120 0 120 125 ns and t = 550 ns CPU CPU SU(SS) t h(SS h(SO) dis(SO) t r(SCK) t f(SCK) LSB OUT BIT1 IN LSB IN and 0.7xV . DD DD ST7DALIF2 Unit ns see note 2 ...
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... ST7DALIF2 Figure 90. SPI slave timing diagram with CPHA=1 SS INPUT t CPHA=0 CPOL=0 CPHA=1 CPOL=1 t a(SO) see MISO OUTPUT note 2 MOSI INPUT Figure 91. SPI master timing diagram SS INPUT CPHA = 0 CPOL = 0 CPHA = 0 CPOL = 1 CPHA = 1 CPOL = 0 CPHA = 1 CPOL = 1 MISO INPUT MOSI See note 2 OUTPUT Note: 1 Measurement points are done at CMOS levels: 0.3xV ...
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... Max V V SSA 10 6 ( =25°C and V -V =5V. They are given only and The first conversion after the enable LOAD 10-Bit A/D Conversion ±1μA 6pF ST72XXX ST7DALIF2 Unit 4 MHz V DDA (3) kΩ pF μs 1/f ADC 1 mA 0.2 ADC ...
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... ST7DALIF2 Table 90. ADC Accuracy with V Symbol Parameter Total unadjusted error | Offset error Gain Error G Differential linearity | error |E | Integral linearity error L 1. Injecting negative current on any of the analog input pins significantly reduces the accuracy of any conversion being performed on any analog input. ...
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... Figure 95. Amplifier output voltage vs. input voltage 156/171 (3) ( LSB IDEAL 701 702 703 704 430mV =8 MHz. then SPEED=0, SLOW=1). CPU Vout (ADC input) Vmax Noise Vmin 0V 0V 430 mV ST7DALIF2 V (LSB ) in IDEAL V (OPAMP less than ADC Vin (OPAMP input) ...
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... ST7DALIF2 Table 91. Amplifier characteristics Symbol V Amplifier operating voltage DD(AMP) V Amplifier input voltage IN Amplifier output offset V OFFSET voltage V Step size for monotonicity STEP Linearity Output Voltage Response Amplified Analog input Gain factor Gain Vmax Output Linearity Max Voltage V Vmin Output Linearity Min Voltage 1 ...
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... Package characteristics 21 Package characteristics In order to meet environmental requirements, ST offers these devices in different grades of ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ® ECOPACK trademark. 158/171 ST7DALIF2 ® ...
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... ST7DALIF2 21.1 Package mechanical data Figure 96. 20-Pin plastic small outline package, 300-mil width Table 93. 20-pin plastic small outline package dimensions Dim α Min Typ Max 2.35 2.65 0.10 0.30 0.33 0.51 0.23 0.32 12.60 13.00 7.40 7.60 1.27 10.00 10.65 0.25 0.75 0° 8° 0.40 1.27 Number of pins Package characteristics h x 45× ...
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... Maximum junction temperature (2) Power dissipation xV ) and P is the port power dissipation depending on the ports used in the DD PORT Value SO20 125 DIP20 63 (1) 150 500 = ( The power dissipation thJA =P +P where P is the chip D INT PORT INT ST7DALIF2 Unit °C/W °C mW ...
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... ST7DALIF2 22 Device configuration Each device is available for production in user programmable versions (FLASH) as well as in factory coded versions (FASTROM). ST7FDALI devices are FLASH versions. ST7PDALI devices are Factory Advanced Service Technique ROM (FASTROM) versions: they are factory programmed FLASH devices. ST7FDALI devices are shipped to customers with a default program memory content (FFh), while FASTROM factory coded parts contain the code supplied by the customer ...
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... RC oscillator off Note: If the RC oscillator is selected, then to improve clock stability and frequency accuracy recommended to place a decoupling capacitor, typically 100 nF, between the V pins as close as possible to the ST7 device. 162/171 Section SEC1 ST7DALIF2 9.6). SEC0 Section 6.5 and ...
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... ST7DALIF2 OPT3:2 = LVD[1:0] Low voltage detection selection These option bits enable the LVD block with a selected threshold as shown in Table 97. LVD threshold configuration LVD Off Highest Voltage Threshold (∼4.1V) Medium Voltage Threshold (∼3.5V) Lowest Voltage Threshold (∼2.8V) OPT1 = WDG SW Hardware or Software Watchdog This option bit selects the watchdog type ...
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... The STMicroelectronics Sales Organization will be pleased to provide detailed information on contractual points. Table 99. Order codes Order code ST7FDALIF2M6 ST7PDALIF2M6 Note: Contact ST sales office for product availability. 164/171 on page 165. Program RAM memory (bytes) (bytes) 8K Flash 384 8K FASTROM 384 ST7DALIF2 Temp. Package range -40° 85° C SO20 -40° 85° C SO20 ...
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... ST7DALIF2 Customer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Injecting a negative current on digital input pins degrades ADC accuracy especially if performed on a pin close to ADC channel in use. 23.5 Clearing active interrupts outside interrupt routine When an active interrupt request occurs at the same time as the related flag or interrupt mask is being cleared, the CC register may be corrupted. Concurrent interrupt context 166/171 ST7DALIF2 ...
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... ST7DALIF2 The symptom does not occur when the interrupts are handled normally, i.e. when: ● The interrupt request is cleared (flag reset or interrupt mask) within its own interrupt routine ● The interrupt request is cleared (flag reset or interrupt mask) within any interrupt routine ● ...
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... Changed section 13.3.1 on page 102: f Changed section 13.7 on page 112 Changed description of WDG HALT option bit (section 15.1 on page 132) Changed description of FMP_R option bit (section 15.1 on page 132) Changed Table 27, “Dedicated STMicroelectronics Development Tools,” on page135 ST7DALIF2 Changes instead of f CLKIN OSC ...
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... ST7DALIF2 Table 100. Document revision history (continued) Date 19-Nov-2004 Revision Reset delay in section 11.1.3 on page 51 changed to 30 µs Altered note 1 for section 13.2.3 on page 101 removing references to RESET Removed sentence relating to an effective change only after overflow for CK[1:0], page 60 MOD00 replaced by 0Ex in Added Note 2 related to Exit from Active halt, ...
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... Replaced soldering information with ECOPACK reference in Section 21 on page 158 Increased precision of package dimensions in inches to 4 decimal digits in Table 93 on page ST7DALIF2 Changes in Figure 12: Clock management block Section 18: 10-bit A/D converter Section 20.7 on page 141 Figure 87 ...
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... ST7DALIF2 Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...