ST7DALIF2 STMicroelectronics, ST7DALIF2 Datasheet - Page 101

• Manufacturer Part Number: ST7DALIF2
• Description: 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, TIMERS, SPI
• Manufacturer: STMicroelectronics

Specifications of ST7DALIF2

• 8 Kbytes Single Voltage Flash Program Memory With Read-out Protection, In-circuit Programming And In-application Programming (icp And Iap). 10k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55°C.
• 256 Bytes Data Eeprom With Read-out Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55°C.
• Clock Sources: Internal 1% RC oscillator, crystal/ceramic resonator or external clock
• Five Power Saving Modes: Halt, Active-Halt, Wait and Slow, Auto Wake Up From Halt

ST7DALIF2
17.4
Figure 45. Serial peripheral interface block diagram
Functional description
A basic example of interconnections between a single master and a single slave is
illustrated in
The MOSI pins are connected together and the MISO pins are connected together. In this
way data is transferred serially between master and slave (most significant bit first).
The communication is always initiated by the master. When the master device transmits
data to a slave device via MOSI pin, the slave device responds by sending data to the
master device via the MISO pin. This implies full duplex communication with both data out
and data in synchronized with the same clock signal (which is provided by the master device
via the SCK pin).
To use a single data line, the MISO and MOSI pins must be connected at each node (in this
case only simplex communication is possible).
Four possible data/clock timing relationships may be chosen (see
slave must be programmed with the same timing mode.
MOSI
MISO
SCK
SS
SOD
bit
Figure
SPIDR
46.
8-Bit Shift Register
Read Buffer
SERIAL CLOCK
GENERATOR
CONTROL
MASTER
Data/Address Bus
Read
Write
7
SPIE
SPIF WCOL
7
SPE
CONTROL
SPR2
OVR
STATE
Serial peripheral interface (SPI)
SPI
Interrupt
request
MODF
MSTR
CPOL
Figure
0
CPHA
SOD
SS
SPICR
SPICSR
49) but master and
SSM
SPR1
0
1
SPR0
SSI
0
0
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