LPC2468 NXP Semiconductors, LPC2468 Datasheet - Page 44

• Manufacturer Part Number: LPC2468
• Description: NXP Semiconductors designed the LPC2468 microcontroller around a 16-bit/32-bitARM7TDMI-S CPU core with real-time debug interfaces that include both JTAG andembedded trace
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC2468
Product data sheet
7.26.1 Reset
7.26.2 Brownout detection
7.26.3 Code security (Code Read Protection - CRP)
7.26 System control
Reset has four sources on the LPC2468: the RESET pin, the Watchdog reset, power-on
reset, and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt trigger input
pin. Assertion of chip Reset by any source, once the operating voltage attains a usable
level, starts the Wake-up Timer (see description in
causing reset to remain asserted until the external Reset is de-asserted, the oscillator is
running, a fixed number of clocks have passed, and the flash controller has completed its
initialization.
When the internal Reset is removed, the processor begins executing at address 0, which
is initially the Reset vector mapped from the Boot Block. At that point, all of the processor
and peripheral registers have been initialized to predetermined values.
The LPC2468 includes 2-stage monitoring of the voltage on the V
voltage falls below 2.95 V, the BOD asserts an interrupt signal to the Vectored Interrupt
Controller. This signal can be enabled for interrupt in the Interrupt Enable Register in the
VIC in order to cause a CPU interrupt; if not, software can monitor the signal by reading a
dedicated status register.
The second stage of low-voltage detection asserts Reset to inactivate the LPC2468 when
the voltage on the V
the flash as operation of the various elements of the chip would otherwise become
unreliable due to low voltage. The BOD circuit maintains this reset down below 1 V, at
which point the power-on reset circuitry maintains the overall Reset.
Both the 2.95 V and 2.65 V thresholds include some hysteresis. In normal operation, this
hysteresis allows the 2.95 V detection to reliably interrupt, or a regularly-executed event
loop to sense the condition.
This feature of the LPC2468 allows user to enable different levels of security in the system
so that access to the on-chip flash and use of the JTAG and ISP can be restricted. When
needed, CRP is invoked by programming a specific pattern into a dedicated flash location.
IAP commands are not affected by the CRP.
There are three levels of the Code Read Protection.
CRP1 disables access to chip via the JTAG and allows partial flash update (excluding
flash sector 0) using a limited set of the ISP commands. This mode is useful when CRP is
required and flash field updates are needed but all sectors can not be erased.
CRP2 disables access to chip via the JTAG and only allows full flash erase and update
using a reduced set of the ISP commands.
Running an application with level CRP3 selected fully disables any access to chip via the
JTAG pins and the ISP. This mode effectively disables ISP override using P2[10]/EINT0
pin, too. It is up to the user’s application to provide (if needed) flash update mechanism
using IAP calls or call reinvoke ISP command to enable flash update via UART0.
All information provided in this document is subject to legal disclaimers.
DD(DCDC)(3V3)
Rev. 6.1 — 6 September 2011
pins falls below 2.65 V. This Reset prevents alteration of
Section 7.25.3 “Wake-up
Single-chip 16-bit/32-bit micro
DD(DCDC)(3V3)
LPC2468
© NXP B.V. 2011. All rights reserved.
timer”),
pins. If this
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