LPC2468 NXP Semiconductors, LPC2468 Datasheet - Page 36

• Manufacturer Part Number: LPC2468
• Description: NXP Semiconductors designed the LPC2468 microcontroller around a 16-bit/32-bitARM7TDMI-S CPU core with real-time debug interfaces that include both JTAG andembedded trace
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC2468
Product data sheet
7.18.1 Features
7.19.1 Features
7.19 I
7.20 I
The LPC2468 contains three I
The I
(SCL), and a Serial Data Line (SDA). Each device is recognized by a unique address and
can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the
capability to both receive and send information (such as memory). Transmitters and/or
receivers can operate in either master or slave mode, depending on whether the chip has
to initiate a data transfer or is only addressed. The I
be controlled by more than one bus master connected to it.
The I
The I
2
2
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C-bus serial I/O controller
S-bus serial I/O controllers
The MCI interface provides all functions specific to the SD/MMC memory card. These
include the clock generation unit, power management control, and command and data
transfer.
Conforms to Multimedia Card Specification v2.11.
Conforms to Secure Digital Memory Card Physical Layer Specification, v0.96.
Can be used as a multimedia card bus or a secure digital memory card bus host. The
SD/MMC can be connected to several multimedia cards or a single secure digital
memory card.
DMA supported through the GPDMA controller.
I
I
devices connected to the same bus lines.
Easy to configure as master, slave, or master/slave.
Programmable clocks allow versatile rate control.
Bidirectional data transfer between masters and slaves.
Multi-master bus (no central master).
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
The I
2
2
2
2
2
C0 is a standard I
C1 and I
C-bus is bidirectional, for inter-IC control using only two wires: a Serial Clock Line
C-bus implemented in LPC2468 supports bit rates up to 400 kbit/s (Fast I
S-bus provides a standard communication interface for digital audio applications.
2
C-bus can be used for test and diagnostic purposes.
2
C2 use standard I/O pins and do not support powering off of individual
All information provided in this document is subject to legal disclaimers.
Rev. 6.1 — 6 September 2011
2
C compliant bus interface with open-drain pins.
2
C-bus controllers.
2
C-bus is a multi-master bus and can
Single-chip 16-bit/32-bit micro
LPC2468
© NXP B.V. 2011. All rights reserved.
2
C-bus).
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