CS8416-CNZ Cirrus Logic Inc, CS8416-CNZ Datasheet - Page 53

• Manufacturer Part Number: CS8416-CNZ
• Description: IC RCVR DGTL 192KHZ 28QFN COMM
• Manufacturer: Cirrus Logic Inc
• Type: Digital Audio Interface Receiverr

Specifications of CS8416-CNZ

• Applications: Digital Audio
• Mounting Type: Surface Mount
• Package / Case: 28-QFN
• Audio Control Type: Digital
• Control Interface: I2C, SPI
• Control / Process Application: AV & DVD Receivers, CD-R, Digital Mixing Consoles
• Supply Voltage Range: 3.13V To 5.25V, 3.13V To 3.46V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1017 - BOARD EVAL FOR CS8416 RCVR
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 598-1723

DS578F3
18.PLL FILTER
18.1
18.2
18.2.1 General
General
An on-chip Phase Locked Loop (PLL) is used to recover the clock from the incoming data stream.
is a simplified diagram of the PLL. When the PLL is locked to an bi-phase encoded input stream, it is updat-
ed at each preamble in the bi-phase encoded stream. This occurs at twice the sampling frequency, F
There are some applications where low jitter in the recovered clock, presented on the RMCK pin, is impor-
tant. For this reason, the PLL has been designed to have good jitter attenuation characteristics, as shown
in
encoded stream to provide lock update information to the PLL. This results in the PLL being immune to data
dependent jitter affects because the preambles do not vary with the data.
The PLL has the ability to lock onto a wide range of input sample rates with no external component changes.
If the sample rate of the input subsequently changes, for example in a varispeed application, the PLL will
only track up to ±12.5% from the nominal center sample rate. The nominal center sample rate is the sample
rate that the PLL first locks onto upon application of an bi-phase encoded data stream or after enabling the
CS8416 clocks by setting the RUN control bit. If the 12.5% sample rate limit is exceeded, the PLL will return
to its wide lock range mode and re-acquire a new nominal center sample rate.
External Filter Components
The PLL behavior is affected by the external filter component values.
mended configuration of the two capacitors and one resistor that comprise the PLL filter. In
component values shown have a high corner frequency jitter attenuation curve, take a short time to lock,
and offer good output jitter performance. Lock times are worst case for an Fsi transition of 192 kHz.
It is important to treat the PLL FLT pin as a low-level analog input. It is suggested that the ground end of
the PLL filter be returned directly to the AGND pin independently of the ground plane.
Figure
INPUT
25. In addition, the PLL has been designed to only use the preambles (PDUR=0) of the bi-phase
and Charge Pump
Comparator
Phase
÷N
Figure 23. PLL Block Diagram
C
R
FLT
FLT
C
RIP
VCO
Figures 5
and
RMCK
6
shows the recom-
Table
CS8416
Figure 23
6, the
S
.
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