CS8416-CNZ Cirrus Logic Inc, CS8416-CNZ Datasheet - Page 12

• Manufacturer Part Number: CS8416-CNZ
• Description: IC RCVR DGTL 192KHZ 28QFN COMM
• Manufacturer: Cirrus Logic Inc
• Type: Digital Audio Interface Receiverr

Specifications of CS8416-CNZ

• Applications: Digital Audio
• Mounting Type: Surface Mount
• Package / Case: 28-QFN
• Audio Control Type: Digital
• Control Interface: I2C, SPI
• Control / Process Application: AV & DVD Receivers, CD-R, Digital Mixing Consoles
• Supply Voltage Range: 3.13V To 5.25V, 3.13V To 3.46V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1017 - BOARD EVAL FOR CS8416 RCVR
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 598-1723

12
2. PIN DESCRIPTION - SOFTWARE MODE
2.1
Name
DGND
AGND
RXP0
RXP1
RXP2
RXP3
RXP4
RXP5
RXP6
RXP7
RST
FILT
Pin
VD
VA
VL
TSSOP Pin Description
Pin #
23
21
22
10
12
13
11
6
7
9
8
4
3
2
1
Analog Power (Input) - Analog power supply. Nominally +3.3 V. This supply should have as little noise
as possible since noise on this pin will directly affect the jitter performance of the recovered clock
Digital Power (Input) – Digital core power supply. Nominally +3.3 V
Logic Power (Input) – Input/Output power supply. Nominally +3.3 V or +5.0 V
Analog Ground (Input) - Ground for the analog circuitry in the chip. AGND and DGND should be con-
nected to a common ground area under the chip.
Digital & I/O Ground (Input) - Ground for the I/O and core logic. AGND and DGND should be connected
to a common ground area under the chip.
Reset (Input) - When RST is low, the CS8416 enters a low power mode and all internal states are reset.
On initial power up, RST must be held low until the power supply is stable, and all input clocks are stable
in frequency and phase.
PLL Loop Filter (Output) - An RC network should be connected between this pin and analog ground.
For minimum PLL jitter, return the ground end of the filter network directly to AGND. See
page 53
Positive AES3/SPDIF Input (Input) - Single-ended or differential receiver inputs carrying AES3 or
S/PDIF encoded digital data. The RXP[7:0] inputs comprise the 8:2 S/PDIF Input Multiplexer. The select
line control is accessed using the Control 4 register (04h). Unused multiplexer inputs should be left float-
ing or tied to AGND. See
ommended input circuits.
AD0 / CS
for more information on the PLL and the external components.
AGND
RXP3
RXP2
RXP1
RXP0
RXP4
RXP5
RXP6
RXP7
RXN
FILT
RST
VA
“External AES3/SPDIF/IEC60958 Receiver Components” on page 49
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28-pin SOIC/TSSOP
Top-Down View
Package
Pin Description
28
27
26
25
24
23
22
21
20
19
18
17
16
15
OLRCK
OSCLK
SDOUT
OMCK
RMCK
VD
DGND
VL
GPO0
GPO1
AD2 / GPO2
SDA / CDOUT
SCL / CCLK
AD1 / CDIN
“PLL Filter” on
CS8416
DS578F3
for rec-