CS8416-CNZ Cirrus Logic Inc, CS8416-CNZ Datasheet

IC RCVR DGTL 192KHZ 28QFN COMM

CS8416-CNZ

Manufacturer Part Number
CS8416-CNZ
Description
IC RCVR DGTL 192KHZ 28QFN COMM
Manufacturer
Cirrus Logic Inc
Type
Digital Audio Interface Receiverr
Datasheet

Specifications of CS8416-CNZ

Applications
Digital Audio
Mounting Type
Surface Mount
Package / Case
28-QFN
Audio Control Type
Digital
Control Interface
I2C, SPI
Control / Process Application
AV & DVD Receivers, CD-R, Digital Mixing Consoles
Supply Voltage Range
3.13V To 5.25V, 3.13V To 3.46V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1017 - BOARD EVAL FOR CS8416 RCVR
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
598-1723
Features
RXP0
RXP1
RXP2
RXP3
RXP4
RXP5
RXP6
RXP7
RXN
Complete EIAJ CP1201, IEC-60958, AES3,
S/PDIF-Compatible Receiver
+3.3 V Analog Supply (VA)
+3.3 V Digital Supply (VD)
+3.3 V or +5.0 V Digital Interface Supply (VL)
8:2 S/PDIF Input MUX
AES/SPDIF Input Pins Selectable in Hardware
Mode
Three General Purpose Outputs (GPO) Allow
Signal Routing
Selectable Signal Routing to GPO Pins
S/PDIF-to-TX Inputs Selectable in Hardware
Mode
Flexible 3-wire Serial Digital Output Port
http://www.cirrus.com
MUX
Receiver
8:2
192 kHz Digital Audio Interface Receiver
VA
AGND FILT
TX Passthrough
Misc.
Control
Clock &
Data
Recovery
RST
RMCK
AES3
S/PDIF
Decoder
Format
Detect
Copyright © Cirrus Logic, Inc. 2007
(All Rights Reserved)
SDA/
CDOUT
VD
See the
on
De-emphasis
Data Buffer
C & U bit
page
32 kHz to 192 kHz Sample Frequency Range
Low-Jitter Clock Recovery
Pin and Microcontroller Read Access to
Channel Status and User Data
SPI™ or I²C
Stand-Alone Hardware Mode
Differential Cable Receiver
On-Chip Channel Status Data Buffer Memories
Auto-Detection of Compressed Audio Input
Streams
Decodes CD Q Sub-Code
OMCK System Clock Mode
SCL/
CCLK
Filter
Control
Port &
Registers
General Description
2.
VL DGND
AD1/
CDIN
®
Control Port Software Mode and
AD0/
CS
OMCK
Serial
Audio
Output
and
MUX
n:3
CS8416
Ordering Information
AUGUST '07
OLRCK
OSCLK
SDOUT
GPO0
GPO1
AD2/GPO2
DS578F3

Related parts for CS8416-CNZ

CS8416-CNZ Summary of contents

Page 1

... AES3 C & U bit S/PDIF Data Buffer Decoder Format Detect SDA/ SCL/ CDOUT CCLK Copyright © Cirrus Logic, Inc. 2007 (All Rights Reserved) CS8416 ® Control Port Software Mode and General Description and Ordering Information 2. VL DGND OMCK Serial Audio Output Control n:3 Port & ...

Page 2

... General Description The CS8416 is a monolithic CMOS device that receives and decodes one of eight stereo pairs of digital audio data according to the IEC60958, S/PDIF, EIAJ CP1201, or AES3 interface standards. The CS8416 has a serial digital audio output port and comprehensive control ability through a selectable control port in Software Mode or through selectable pins in Hardware Mode ...

Page 3

... CHANNEL STATUS AND USER-DATA HANDLING ....................................................................... 32 11.1 Software Mode ............................................................................................................................ 32 11.2 Hardware Mode ........................................................................................................................... 32 12. CONTROL PORT DESCRIPTION ..................................................................................................... 33 12.1 SPI Mode ..................................................................................................................................... 33 12.2 I²C Mode ...................................................................................................................................... 34 13. CONTROL PORT REGISTER QUICK REFERENCE ....................................................................... 35 14. CONTROL PORT REGISTER DESCRIPTIONS .............................................................................. 36 14.1 Memory Address Pointer (MAP) .................................................................................................. 36 14.2 Control0 (00h) ............................................................................................................................. 36 14.3 Control1 (01h) ............................................................................................................................. 37 DS578F3 CS8416 3 ...

Page 4

... Q-Channel Subcode (0Eh - 17h) ............................................................................................... 44 14.16 OMCK/RMCK Ratio (18h) 14.17 Channel Status Registers (19h - 22h) ....................................................................................... 45 14.18 IEC61937 PC/PD Burst Preamble (23h - 26h) .......................................................................... 45 14.19 CS8416 I.D. and Version Register (7Fh) ................................................................................... 45 15. HARDWARE MODE .......................................................................................................................... 46 15.1 Serial Audio Port Formats ........................................................................................................... 46 15.2 Hardware Mode Function Selection ............................................................................................ 46 15 ...

Page 5

... Figure 25. Jitter Attenuation Characteristics of PLL................................................................................... 55 LIST OF TABLES Table 1. Typical Delays by Frequency Values ........................................................................................... 26 Table 2. Clock Switching Output Clock Rates............................................................................................ 28 Table 3. GPO Pin Configurations............................................................................................................... 29 Table 4. Hardware Mode Start-Up Pin Conditions ..................................................................................... 47 Table 5. Hardware Mode Serial Audio Format Select................................................................................ 48 Table 6. External PLL Component Values ................................................................................................. 54 DS578F3 CS8416 5 ...

Page 6

... Notes: 1. Transient currents 100 mA will not cause SCR latch-up. 6 Symbol Min VA 3.13 VD 3.13 VL 3.13 Commercial Grade T A Automotive Grade Symbol VA, VD,VL (Note stg CS8416 Typ Max Units 3.3 3.46 V 3.3 3.46 V 3.3 or 5.0 5.25 V -10 - +70 °C -40 - +85 Min Max Units - 6 ± ...

Page 7

... Low-Level Input Voltage, except RXP[7:0], RXN DS578F3 Symbol Min Typ 11.8 Symbol Min Typ 150 Symbol Min V (VL -0.3 IL CS8416 Max Units μ μ μ μ Max Units μ A ±0.5 200 mVpp 1.0 V Max Units - V 0.5 V (VL) + 0 ...

Page 8

... RMCK/OMCK Maximum Frequency Notes: 5. Typical RMS cycle-to-cycle jitter. 6. Duty cycle when clock is recovered from biphase encoded input. 7. Duty cycle when OMCK is switched over for output on RMCK pF) L Symbol Min 200 30 (Note 5) - (Note 6) 45 (Note CS8416 Typ Max Units μ 200 kHz 200 - ps RMS ...

Page 9

... utp ut) Figure 1. Audio Port Master Mode Timing DS578F3 = 20 pF) L Symbol (Note 8) (Note 8) t (Note (Notes 8,9,10) t (Notes 8,9,11) t OLRCK (input) OSCLK (input SDOUT Figure 2. Audio Port Slave Mode and Data Input CS8416 Min Typ Max dpd smd lmd - sckw t 14 ...

Page 10

... For f <1 MHz. sck CS CCLK CDIN CDOUT pF) L Symbol (Note 12) f sck t csh t css t scl t sch t dsu (Note 13 (Note 14 (Note 14 scl t sch t css dsu Figure 3. SPI Mode Timing CS8416 Min Max Unit 0 6.0 MHz 1.0 - µ 100 ns - 100 ns t csh DS578F3 ...

Page 11

... Repeated Start t high t t sud t sust hdd Figure 4. I²C Mode Timing CS8416 Min Max Unit - 100 kHz 4.7 - µs 4.0 - µs 4.7 - µs 4.0 - µs 4.7 - µ 250 - ns - 1000 ...

Page 12

... DGND common ground area under the chip. Reset (Input) - When RST is low, the CS8416 enters a low power mode and all internal states are reset. RST 9 On initial power up, RST must be held low until the power supply is stable, and all input clocks are stable in frequency and phase ...

Page 13

... SPI Control Port Mode. With no falling edge, the CS8416 defaults to I²C Mode. In I²C Mode, AD0 is AD0 / chip address pin. In SPI Mode used to enable the control port interface on the CS8416. See the “Control Port Description” section on page Address Bit 1 (I²C) / Serial Control Data in (SPI) (Input I²C Mode, AD1 is a chip address pin. In ...

Page 14

... DGND common ground area under the chip. Reset (Input) - When RST is low, the CS8416 enters a low power mode and all internal states are reset. RST 6 On initial power up, RST must be held low until the power supply is stable, and all input clocks are stable in frequency and phase ...

Page 15

... SPI Control Port Mode. With no falling edge, the CS8416 defaults to I²C Mode. In I²C Mode, AD0 is AD0 / chip address pin. In SPI Mode used to enable the control port interface on the CS8416. See the “Control Port Description” section on page Address Bit 1 (I²C) / Serial Control Data in (SPI) (Input I²C Mode, AD1 is a chip address pin. In ...

Page 16

... DGND 22 nected to a common ground area under the chip. Reset (Input) - When RST is low, the CS8416 enters a low power mode and all internal states are RST 9 reset. On initial power up, RST must be held low until the power supply is stable, and all input clocks are stable in frequency and phase ...

Page 17

... OLRCK. Also used to select the frequency of RMCK to either 256*F DS578F3 Pin Description “OMCK System Clock Mode” on page ) when the U pin is pulled down kΩ when the U pin is pulled kΩ s 31. This pin is also used to select the serial port format (SFSEL1) at CS8416 28. or 128*F at reset ...

Page 18

... DGND 19 nected to a common ground area under the chip. Reset (Input) - When RST is low, the CS8416 enters a low power mode and all internal states are RST 6 reset. On initial power up, RST must be held low until the power supply is stable, and all input clocks are stable in frequency and phase ...

Page 19

... PAD DS578F3 Pin Description for recommended input circuits. “OMCK System Clock Mode” on page ) when the U pin is pulled down kΩ when the U pin is pulled kΩ s 31. This pin is also used to select the serial port format (SFSEL1) at CS8416 “External 28. or 128*F at reset ...

Page 20

... AD1 / CDIN AD2/GPO2 SCL / CCLK SDA / CDOUT RST AGND FILT DGND R FLT C RIP C FLT *** and “External AES3/SPDIF/IEC60958 Receiver Components” on page 49 CS8416 +3 0.1 F μ 47k Ω Serial Audio Input Device Clock Control Clock Source External Interface Table 6 on page 54 for PLL DS578F3 ...

Page 21

... RXSEL1 RMCK TXSEL0 TXSEL1 OMCK * NV/RERR * AUDIO * 96KHZ * TX * RCBL * AGND FILT DGND R FLT C RIP C FLT **** and “External AES3/SPDIF/IEC60958 Receiver Components” on page 49 CS8416 +3 μ Serial Audio Input Device 47k Ω Clock Control Clock Source External Interface Table 6 on page 54 for PLL 21 ...

Page 22

... The pins are then switched to be outputs. This mechanism allows output pins to be used to set alternative modes in the CS8416 by connecting Ω resistor to between the pin and either VL (HI) or DGND (LO). For each mode, every start-up option select pin MUST have an external pull-up or pull-down resistor as there are no internal pull-up or pull-down resistors for these startup conditions (except for TX, which has an internal pull-down) ...

Page 23

... The CS8416 provides an 8:2 multiplexer to select between eight inputs for decoding and to allow an input signal to be routed to an output of the CS8416. Input data can be either differential or single-ended. A low jitter clock is re- covered from the incoming data using a PLL. The decoded audio data is output through a configurable, 3-wire serial audio output port. The channel status and Q-channel subcode portion of the user data are assembled in registers and may be accessed through an SPI or I² ...

Page 24

... When in slave mode, the serial audio output port cannot be set for right-justified data. The CS8416 allows immediate mute of the serial audio output port audio data by the MUTESAO bit of Control Register 1. For more information about serial audio formats, refer to the Cirrus Logic applications note AN282, “The 2-Channel Serial Audio Interface: A Tutorial” ...

Page 25

... When the serial output port is configured as slave, depending on the relative frequency of OLRCK to the input AES3 data (Z/X) preamble frequency, the data will be slipped or repeated at the output of the CS8416. After a fixed delay from the Z/X preamble (a few periods of the internal clock, which is running at 256Fs), ...

Page 26

... OLRCK (depending on the setting of SOLRPOL in register 05h) will be treated as being sam- pled at the same time. Since the CS8416 has no control of the OLRCK in slave mode, the latency of the data through the part will be a multiple of 1/Fs plus the delay between OLRCK and the preambles. ...

Page 27

... RXP0 to RXP7 and a common RXN, a PLL based clock recovery circuit, and a decoder which separates the audio data from the channel status and user data. External components are used to terminate the incoming data cables and isolate the CS8416. These components are detailed in “ ...

Page 28

... MHz s 256*F s 256*F 11.2896 MHz s for a general description of the PLL, selection of recommended PLL filter Figures 5 and 6 show the recommended configuration of the two CS8416 RMCK OSCLK OLRCK 3.072 MHz 48 kHz 3.072 MHz 48 kHz ~375 kHz ~187.5 kHz ~2.925 kHz 2.8224 MHz 44 ...

Page 29

... Three General Purpose Outputs (GPO) are provided to allow the equipment designer flexibility in configuring the CS8416. Fourteen signals are available to be routed to any of the GPO pins. The outputs of the GPO pins are set through the GPOxSEL[3:0] bits in the Control2 (02h) and Control3 (03h) registers. All GPO pins default to GND after reset ...

Page 30

... AND STATUS REPORTING 10.1 General While decoding the incoming bi-phase encoded data stream, the CS8416 has the ability to identify various error conditions. 10.1.1 Software Mode Software Mode allows the most flexibility in reading errors. When unmasked, bits in the Receiver Error register (0Ch) indicate the following errors: 1. QCRC – ...

Page 31

... CS8416. However, certain non-audio sources, such as AC-3™ or MPEG encoders, may not adhere to this convention, and the bit may not be properly set. The CS8416 AES3 receiver can detect such non-audio data through the use of an autodetect module. The autodetect module is similar to autodetect software used in Cirrus Logic DSPs ...

Page 32

... C/U output. – VLRCK duty cycle is 50%. VLRCK frequency is always equal to the incoming 32 describes Channel Status and User data control. “Hardware Mode Function Selection” on page 46 to configure these pins.. Figure 10. C/U Data Outputs CS8416 Figure 10 il- and DS578F3 ...

Page 33

... However, to avoid potential interference problems, the control port pins should remain static if no op- eration is required. The control port has 2 modes: SPI and I²C, with the CS8416 acting as a slave device. SPI Mode is selected if there is a high to low transition on the AD0/CS pin, after the RST pin has been brought high. I²C Mode is selected by con- necting the AD0/CS pin through a resistor DGND, thereby permanently selecting the desired AD0 bit ad- dress state ...

Page 34

... CS pin. Pins AD0 and AD1 form the two least significant bits of the chip address and should be con- nected through a resistor DGND as desired. The GPO2 pin is used to set the AD2 bit by connecting Ω resistor from the GPO2 pin DGND. The states of the pins are sensed while the CS8416 is being reset. ...

Page 35

... FRAME FRAME FRAME ORR6 ORR5 ORR4 AC0[6] AC0[5] AC0[4] AC1[6] AC1[5] AC1[4] AC2[6] AC2[5] AC2[4] AC3[6] AC3[5] AC3[4] AC4[6] AC4[5] AC4[4] CS8416 PDUR TRUNC Reserved Reserved HOLD1 HOLD0 RMCKF GPO0SEL3 GPO0SEL2 GPO0SEL1 GPO0SEL0 RXSEL0 TXSEL2 TXSEL1 TXSEL0 SOJUST SODEL SOSPOL SOLRPOL VM ...

Page 36

... PC0[6] PC0[5] PC0[4] PC1[6] PC1[5] PC1[4] PD0[6] PD0[5] PD0[4] PD1[6] PD1[5] PD1[4] ID2 ID1 ID0 MAP4 MAP3 PDUR CS8416 BC0[3] BC0[2] BC0[1] BC0[0] BC1[3] BC1[2] BC1[1] BC1[0] BC2[3] BC2[2] BC2[1] BC2[0] BC3[3] BC3[2] BC3[1] BC3[0] BC4[3] BC4[2] BC4[1] BC4[0] PC0[3] PC0[2] ...

Page 37

... HOLD[1:0] – Determine how received audio sample is affected when a receive error occurs Default = ‘00’ 00 – hold last audio sample. 01 – replace the current audio sample with all zeros (mute). 10- do not change the received audio sample reserved DS578F3 INT0 HOLD1 CS8416 HOLD0 RMCKF CHS 37 ...

Page 38

... Thus it is impossible to have de-emphasis applied to one channel but not the other. The de-emphasis filter is turned off if the audio data is detected to be non-audio data. GPO0SEL[3:0] – GPO0 Source select. See Default = ‘0000’ GPO0SEL3 Figure 14 “General Purpose Outputs” on page CS8416 2 1 GPO0SEL2 GPO0SEL1 GPO0SEL0 for De-emphasis filter response. 29. DS578F3 0 ...

Page 39

... Internal clocks are stopped. Internal state machines are reset. The fully static control port is operational, allowing registers to be read or changed. Power consumption is low Normal part operation. This bit must be written to the 1 state to allow the CS8416 to begin operation. All input clocks should be stable in frequency and phase when RUN is set to 1. ...

Page 40

... MSB of SDOUT data occurs in the first OSCLK period after the OLRCK edge MSB of SDOUT data occurs in the second OSCLK period after the OLRCK edge. SOSPOL - OSCLK clock polarity Default = ‘0’ SDOUT is sampled on rising edges of OSCLK SDOUT is sampled on falling edges of OSCLK SORES0 SOJUST . CS8416 SODEL SOSPOL SOLRPOL DS578F3 ...

Page 41

... INT[1:0] bits. These registers default to 00h Rising edge active 01 - Falling edge active 10 - Level active 11 - Reserved DS578F3 UNLOCKM DETCM CCHM DETC1 CCH1 DETC0 CCH0 CS8416 CONFM BIPM PARM RERRM QCHM FCHM “General Purpose Outputs” on page RERR1 QCH1 FCH1 RERR0 QCH0 FCH0 29 ...

Page 42

... PCM, DTS_LD, DTS_CD and IEC61937 are mutually exclusive. A ‘1’ indicated the condition was detected. PCM – Uncompressed PCM data was detected. IEC61937 – IEC61937 data was detected. DTS_LD – DTS_LD data was detected AUX0 PRO DTS_LD DTS_CD CS8416 COPY ORIG EMPH Reserved DGTL_SIL 96KHZ DS578F3 ...

Page 43

... Confidence error. The logical OR of UNLOCK and BIP. The input data stream may be near error condi- tion due to jitter degradation. BIP - Bi-phase error bit. Updated on sub-frame boundaries error Bi-phase error. This indicates an error in the received bi-phase coding. PAR - Parity bit. Updated on sub-frame boundaries error Parity error. DS578F3 UNLOCK V CS8416 CONF BIP PAR 43 ...

Page 44

... CONTROL ADDRESS TRACK TRACK INDEX INDEX MINUTE MINUTE SECOND SECOND FRAME FRAME ZERO ZERO ABS FRAME ABS FRAME CS8416 2 1 RERR QCH FCH “Slip/Repeat Behavior” on “Channel Status Buffer Management” ADDRESS ADDRESS ADDRESS TRACK TRACK TRACK INDEX INDEX INDEX ...

Page 45

... Burst Preamble PD Byte 0 26h Burst Preamble PD Byte 1 14.19 CS8416 I.D. and Version Register (7Fh ID3 ID2 ID[3: code for the CS8416. Permanently set to 0010 VER[3:0] = 0001 (revision A) VER[3:0] = 0010 (revision B) VER[3:0] = 0011 (revision C) VER[3 0111 (revision D) VER[3:0] = 1111 (revision E) DS578F3 5 4 ...

Page 46

... MODE The CS8416 has a Hardware Mode that allows the device to operate without a microcontroller. Hardware Mode is selected by connecting the 47 k Ω pull-up/down resistor on the SDOUT pin to ground. Various pins change function in Hardware Mode, described in Section 15.2 “Hardware Mode Function Selection” on page Hardware Mode data flow is shown in to the serial audio output port ...

Page 47

... Control3 Register (03h) GPO1SEL[3:0] = N/A GPO2SEL[3:0] = N/A DS578F3 Pull Function Software Mode Serial Port Master Mode Serial Format Select 1 (SFSEL1)=1 Serial Format Select 0 (SFSEL0)=1 RMCK Frequency=128*F s Higher Phase Detector update rate. Emphasis Audio Match On RERR Selected Figure 14 CS8416 s for the de-emphasis filter re- 47 ...

Page 48

... Table 5. Hardware Mode Serial Audio Format Select Receiver Error Mask register (06h) QCRCM = 0 CRCM = 0 UNLOCKM = 1 CONFM = 1 BIPM = 1 PARM = set by NV/RERR pull-up/down after reset. Registers 07h through 7Fh do not have Hardware Mode equivalent settings. 48 Table 5 SOSF SORES[1:0] SOJUST CS8416 for bit settings. SODEL SOSPOL SOLRPOL DS578F3 ...

Page 49

... AES3 Receiver External Components The CS8416 AES3 receiver is designed to accept both the professional and consumer interfaces. The dig- ital audio specifications for professional use call for a balanced receiver, using XLR connectors, with 110 Ω ± 20% impedance. The XLR connector on the receiver should have female pins with a male shell. ...

Page 50

... Figure 18. Consumer Input Circuit TTL/CMOS Ω CS8416 7 5 Ω RXP0 7 5 Ω RXN Figure 19. S/PDIF MUX Input Circuit Gate 0.01 μF 0.01 μF Figure 20. TTL/CMOS Input Circuit CS8416 .0 1 μ Ω μ Ω μ Ω μ F CS8416 RXP0 RXN DS578F3 ...

Page 51

... AES3 Channel Status (C) Bit Management The CS8416 contains sufficient RAM to store the first 5 bytes of C data for both A and B channels ( bits). The user may read from this buffer’s RAM through the control port. The buffering scheme involves two buffers, named D and E, as shown in represents the first bit in the serial C data stream ...

Page 52

... From Data AES3 Buffer Receiver D C Data Serial Output Figure 21. Channel Status Data Buffer Structure interrupt occurs Return Figure 22. Flowchart for Reading the E Buffer 8-bits 8-bits 5 words 19 words E Optionally set inhibit Read E data If set, clear inhibit CS8416 Control Port Registers DS578F3 ...

Page 53

... PLL first locks onto upon application of an bi-phase encoded data stream or after enabling the CS8416 clocks by setting the RUN control bit. If the 12.5% sample rate limit is exceeded, the PLL will return to its wide lock range mode and re-acquire a new nominal center sample rate. ...

Page 54

... The external PLL component values are listed in Range (kHz 192 54 FLT , C FLT 1000 C pF RIP C .1µF FLT Table FLT FLT 3 k Ω Table 6. External PLL Component Values CS8416 , an X7R dielectric is preferred. Avoid ca- Figure and the 1000 pF decoupling ca- FLT RIP C Settling Time RIP DS578F3 ...

Page 55

... Jitter Attenuation Shown in Figure 25 is the jitter attenuation plot. The AES3 and IEC60958-4 specifications state a maxi- mum jitter gain or peaking Figure 25. Jitter Attenuation Characteristics of PLL DS578F3 itter F requency (Hz) CS8416 ...

Page 56

... JEDEC #: MS-013 Controlling Dimension is Millimeters CS8416 MILLIMETERS MIN NOM MAX 2.35 2.50 2.65 0.10 0.20 0.30 0.33 0.42 0.51 0.23 0.28 ...

Page 57

... BSC 9.60 BSC 0.256 6.30 0.177 4. 0.029 0.50 4° 8° 0° JEDEC #: MO-153 Controlling Dimension is Millimeters. Symbol θ 4 Layer Board JA CS8416 1 E1 END VIEW L MILLIMETERS NOTE NOM MAX -- 1.20 0.10 0.15 0.90 1.00 0.245 0.30 9.70 BSC 9.80 BSC 6.40 6 ...

Page 58

... JEDEC #: MO-220 Controlling Dimension is Millimeters. Symbol 2 Layer Board θ Layer Board CS8416 Bottom View MILLIMETERS NOM MAX -- 1.00 -- 0.05 0.23 0.30 5.00 BSC 3.15 3.20 5.00 BSC 3.15 3 ...

Page 59

... Order# Rail CS8416-CSZ 28-SOIC Tape and CS8416-CSZR Reel Rail CS8416-CZZ 28-TSSOP Tape and CS8416-CZZR Reel Rail CS8416-CNZ 28-QFN Tape and CS8416-CNZR Reel Rail CS8416-DSZ 28-SOIC Tape and CS8416-DSZR Reel Rail CS8416-DZZ 28-TSSOP Tape and CS8416-DZZR Reel Rail CS8416-DNZ 28-QFN Tape and ...

Page 60

... Audio Output Example Formats” on page page 28 text referencing VCO idle frequency. Figure 10 on page 32. to reflect the Auto-Increment function of the MAP. “Pin Description - Software Mode” on page 12 16. and “QFN Thermal Characteristics” on page www.cirrus.com. CS8416 8. 24. and “Pin 58. DS578F3 ...

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