SAM9G20 Atmel Corporation, SAM9G20 Datasheet - Page 76
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SAM9G20
Manufacturer Part Number
SAM9G20
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(248 pages)
2.SAM9261.pdf
(1274 pages)
3.SAM9261.pdf
(43 pages)
4.SAM9G20.pdf
(42 pages)
5.SAM9G20.pdf
(832 pages)
Specifications of SAM9G20
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
1
Uart
7
Ssc
1
Ethernet
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
Yes
Adc Channels
4
Adc Resolution (bits)
10
Adc Speed (ksps)
95
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9261 PDF datasheet
- SAM9261 PDF datasheet #2
- SAM9261 PDF datasheet #3
- SAM9G20 PDF datasheet #4
- SAM9G20 PDF datasheet #5
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Memory Management Unit
3.2.6
3-12
Fine page table descriptor
31
Coarse page table descriptor bit assignments are described in Table 3-5.
A fine page table descriptor provides the base address of a page table that contains
second-level descriptors for large page, small page, or tiny page accesses. Fine page
tables have 1024 entries, splitting the 1MB that the table describes into 1KB blocks.
Figure 3-7 shows the format of a fine page table descriptor.
If a fine page table descriptor is returned from the first-level fetch, a second-level fetch
is initiated.
Bits
[31:10]
[9]
[8:5]
[4]
[3:2]
[1:0]
Copyright © 2001-2003 ARM Limited. All rights reserved.
Note
Fine page table base address
Description
These bits form the base for referencing the second-level descriptor (the coarse
page table index for the entry is derived from the MVA)
Always written as 0
These bits specify one of the 16 possible domains (held in the domain access
control registers) that contain the primary access controls
Always written as 1
Always written as 0
These bits must be 01 to indicate a coarse page table descriptor
Table 3-5 Coarse page table descriptor bits
Figure 3-7 Fine page table descriptor
12 11
SBZ
9 8
Domain
5 4 3 2 1 0
1 SBZ 1
ARM DDI0198D
1
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