SAM9G20 Atmel Corporation, SAM9G20 Datasheet - Page 55

• Manufacturer Part Number: SAM9G20
• Manufacturer: Atmel Corporation

Specifications of SAM9G20

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 7
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 95
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

ARM DDI0198D
31
The first four bits of this register determine the L bit for the associated cache way. The
Opcode_2 field of the MRC or MCR instruction determines whether the instruction or
data lockdown register is accessed:
Opcode_2 = 0
Opcode_2 = 1
You can use the instructions shown in Table 2-20 to access the Cache Lockdown
Register.
You must only modify the Cache Lockdown Register using a read-modify-write
sequence. For example:
This sequence sets the L bit to 1 for way 0 of the ICache. The format of the cache
lockdown register c9 is shown in Figure 2-12.
Copyright © 2001-2003 ARM Limited. All rights reserved.
SBZ/UNP
Function
Read DCache Lockdown Register
Write DCache Lockdown Register
Read ICache Lockdown Register
Write ICache Lockdown Register
Selects the DCache lockdown register.
Selects the ICache lockdown register.
Table 2-20 Cache Lockdown Register instructions
Figure 2-12 Cache Lockdown Register c9 format
16 15
SBO
Data
L bits
L bits
L bits
L bits
Instruction
Programmer’s Model
4 3
(cache ways
0 to 3)
L bits
0
2-27