SAM9G20 Atmel Corporation, SAM9G20 Datasheet - Page 16

• Manufacturer Part Number: SAM9G20
• Manufacturer: Atmel Corporation

Specifications of SAM9G20

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 7
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 95
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Preface
About this manual
Product revision status
Intended audience
Using this manual
xvi
This is the Technical Reference Manual for the ARM926EJ-S processor.
The rnpn identifier indicates the revision status of the product described in this manual,
where:
rn
pn
This document has been written for experienced hardware and software engineers who
have previous experience of ARM products, and who wish to use an ARM926EJ-S
processor in their system design.
This document is organized into the following chapters:
Chapter 1 Introduction
Chapter 2 Programmer’s Model
Chapter 3 Memory Management Unit
Chapter 4 Caches and Write Buffer
Chapter 5 Tightly-Coupled Memory Interface
Copyright © 2001-2003 ARM Limited. All rights reserved.
Identifies the major revision of the product.
Identifies the minor revision or modification status of the product.
Read this chapter for an overview of the ARM926EJ-S processor.
Read this chapter for details of the programmer’s model and
ARM926EJ-S registers.
Read this chapter for details of the Memory Management Unit (MMU)
and address translation process and how to use the CP15 register to
enable and disable the MMU.
Read this chapter for a description of the instruction cache, the data
cache, the write buffer, and the physical address tag RAM.
Read this chapter for a description of the Tightly-Coupled Memory
(TCM) interface and how to use the CP15 region register to enable and
disable the caches. It includes examples on how various RAM types can
be connected.
ARM DDI0198D