SAM9G20 Atmel Corporation, SAM9G20 Datasheet - Page 31
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SAM9G20
Manufacturer Part Number
SAM9G20
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(248 pages)
2.SAM9261.pdf
(1274 pages)
3.SAM9261.pdf
(43 pages)
4.SAM9G20.pdf
(42 pages)
5.SAM9G20.pdf
(832 pages)
Specifications of SAM9G20
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
1
Uart
7
Ssc
1
Ethernet
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
Yes
Adc Channels
4
Adc Resolution (bits)
10
Adc Speed (ksps)
95
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9261 PDF datasheet
- SAM9261 PDF datasheet #2
- SAM9261 PDF datasheet #3
- SAM9G20 PDF datasheet #4
- SAM9G20 PDF datasheet #5
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2.2
ARM DDI0198D
Summary of ARM926EJ-S system control coprocessor (CP15) registers
CP15 defines 16 registers. Table 2-1 shows the read and write functions of the registers.
Register
0
0
0
1
2
3
4
5
5
6
7
8
9
9
10
11 and 12
13
13
14
15
a. Register locations 0, 5, and 13 each provide access to more than one register. The register
b. Register location 9 provides access to more than one register. The register accessed depends
Copyright © 2001-2003 ARM Limited. All rights reserved.
accessed depends on the value of the
on the value of the
Reads
ID code
Cache type
TCM status
Control
Translation table base
Domain access control
Reserved
Data fault status
Instruction fault status
Fault address
Cache operations
Unpredictable
Cache lockdown
TCM region
TLB lockdown
Reserved
FCSE PID
Context ID
Reserved
Test configuration
a
field. See the register descriptions for details.
a
a
a
a
a
b
a
field.
Table 2-1 CP15 register summary
Writes
Unpredictable
Unpredictable
Unpredictable
Control
Translation table base
Domain access control
Reserved
Data fault status
Instruction fault status
Fault address
Cache operations
TLB operations
Cache lockdown
TCM region
TLB lockdown
Reserved
FCSE PID
Context ID
Reserved
Test configuration
a
a
a
Programmer’s Model
a
2-3
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