SAM9G20 Atmel Corporation, SAM9G20 Datasheet - Page 209
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SAM9G20
Manufacturer Part Number
SAM9G20
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(248 pages)
2.SAM9261.pdf
(1274 pages)
3.SAM9261.pdf
(43 pages)
4.SAM9G20.pdf
(42 pages)
5.SAM9G20.pdf
(832 pages)
Specifications of SAM9G20
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
1
Uart
7
Ssc
1
Ethernet
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
Yes
Adc Channels
4
Adc Resolution (bits)
10
Adc Speed (ksps)
95
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9261 PDF datasheet
- SAM9261 PDF datasheet #2
- SAM9261 PDF datasheet #3
- SAM9G20 PDF datasheet #4
- SAM9G20 PDF datasheet #5
- Current page: 209 of 248
- Download datasheet (2Mb)
ARM DDI0198D
Bits
[31:20]
[19]
[18]
[17]
[16]
[15]
[14]
[13]
[12:0]
Function or name
Reserved
Test and clean all
Abort data TLB miss
Abort instruction TLB miss
Disable NC instruction prefetching
Disable block-level clock gating
Disable NCB stores (force NCNB)
MMU disabled, DCache enabled
behavior
Reserved
The reset state of the Debug Override Register is
Bit 13, MMU disabled, DCache enabled behavior
Bit 14, disable NCB stores (force NCNB)
Copyright © 2001-2003 ARM Limited. All rights reserved.
This bit changes the behavior when the MMU is disabled but the DCache
is enabled. During normal operation, if the MMU is disabled, all data
accesses are treated as being NCNB. If Bit 13 is set with the MMU
disabled, and the DCache is enabled, all data accesses are treated as WT.
This behavior can be overridden using the memory region register.
You can use this bit to force all NCB stores to be treated as NCNB stores
at level one. This bit overrides the settings in both the MMU page tables
and the memory region remap register.
Note
Description
Read = Unpredictable
Write = Should Be Zero
0 = Default behavior for test and clean instructions
1 = Modifies the behavior of test and clean, and test, clean, and
invalidate instructions so that they act on the complete cache
0 = Do not abort DTLB miss
1 = Abort DTLB miss
0 = Do not abort ITLB miss
1 = Abort ITLB miss
0 = Enable prefetching
1 = Disable prefetching
0 = Enable block-level clock gating
1 = Disable block-level clock gating
0 = Enable NCB stores
1 = Disable NCB stores (force NCNB)
0 = If MMU disabled. level one access NCNB
1 = If MMU disabled and DCache enabled level one access WT
Read = Unpredictable
Write = Should Be Zero
Table B-1 Debug Override Register
.
CP15 Test and Debug Registers
B-3
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