SAM9G20 Atmel Corporation, SAM9G20 Datasheet - Page 112
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SAM9G20
Manufacturer Part Number
SAM9G20
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(248 pages)
2.SAM9261.pdf
(1274 pages)
3.SAM9261.pdf
(43 pages)
4.SAM9G20.pdf
(42 pages)
5.SAM9G20.pdf
(832 pages)
Specifications of SAM9G20
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
1
Uart
7
Ssc
1
Ethernet
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
Yes
Adc Channels
4
Adc Resolution (bits)
10
Adc Speed (ksps)
95
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9261 PDF datasheet
- SAM9261 PDF datasheet #2
- SAM9261 PDF datasheet #3
- SAM9G20 PDF datasheet #4
- SAM9G20 PDF datasheet #5
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- Download datasheet (2Mb)
Tightly-Coupled Memory Interface
5.2
5.2.1
5-4
TCM interface signals
Data interface signals
The TCM interface is designed to be compatible the timings of standard ASIC SRAM
components, allowing connection to single cycle SRAM with minimal interfacing logic
required. For standard SRAM the chip-select, address, and write data/control signals are
setup in one cycle, and the read or write operation takes place in the next cycle.
The signals in the DTCM interface can be grouped by function into four categories.
•
•
•
•
Control signals
The control signals for the data interface are:
DRCS
DRCS is used to indicate that an access will commence in the following cycle. For
simple zero wait state TCM systems the DRCS signals corresponds directly to a
memory chip select signal. For more complex systems DRCS corresponds to a memory
request signal.
Copyright © 2001-2003 ARM Limited. All rights reserved.
Control signals
—
—
—
Address and attribute signals
—
—
—
—
Data signals
—
—
DMA signals
—
—
—
DRCS
DRWAIT
DRIDLE
DRSEQ
DRADDR[17:0]
DRWBL[3:0]
DRnRW
DRRD[31:0]
DRWD[31:0]
DRDMAEN
DRDMACS
DRDMAADDR[17:0].
ARM DDI0198D
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