SAM9261 Atmel Corporation, SAM9261 Datasheet - Page 8
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SAM9261
Manufacturer Part Number
SAM9261
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9260.pdf
(290 pages)
2.SAM9261.pdf
(248 pages)
3.SAM9261.pdf
(749 pages)
4.SAM9261.pdf
(44 pages)
5.SAM9261.pdf
(1274 pages)
6.SAM9261.pdf
(43 pages)
Specifications of SAM9261
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
240 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
1
Uart
4
Ssc
3
Sd / Emmc
1
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
160
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.08 to 1.32
Fpu
No
Mpu / Mmu
No/Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9260 PDF datasheet
- SAM9261 PDF datasheet #2
- SAM9261 PDF datasheet #3
- SAM9261 PDF datasheet #4
- SAM9261 PDF datasheet #5
- SAM9261 PDF datasheet #6
- Current page: 8 of 290
- Download datasheet (5Mb)
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Table 4-5
Table 4-6
Table 4-7
Table 4-8
Table 4-9
Table 4-10
Table 4-11
Table 4-12
Table 4-13
Table 4-14
Table 4-15
Table 4-16
Table 6-1
Table 6-2
Table 7-1
Table 8-1
Table 8-2
Table 8-3
Table 8-4
Table 8-5
Table 8-6
Table 8-7
Table 8-8
Table 8-9
Table 8-10
Table 8-11
Table 8-12
Table 8-13
Table 8-14
Table 8-15
Table 8-16
Table 8-17
Table 8-18
Table 8-19
Table 8-20
Table 8-21
Table 8-22
Table 8-23
Table 8-24
Table 8-25
Table 8-26
Table 8-27
Table 8-28
Table 8-29
Table 8-30
Table 8-31
Table 8-32
Copyright © 2000 ARM Limited. All rights reserved.
Halfword accesses ....................................................................... 4-7
Cycle types ................................................................................... 4-8
Burst types ................................................................................. 4-10
Transfer widths ........................................................................... 4-16
DnTRANS encoding ................................................................... 4-16
Transfer size encoding ............................................................... 4-21
Significant address bits .............................................................. 4-21
Word accesses ........................................................................... 4-22
Halfword accesses ..................................................................... 4-22
Byte accesses ............................................................................ 4-22
Cycle types ................................................................................. 4-24
Burst types ................................................................................. 4-28
Handshake signals ....................................................................... 6-7
Handshake signal connections ................................................... 6-20
Coprocessor 14 register map ..................................................... 7-16
Key to tables ................................................................................. 8-3
ARM instruction cycle counts ....................................................... 8-3
Key to cycle timing tables ............................................................. 8-7
Branch and ARM branch with link cycle timings ........................... 8-8
Thumb branch with link cycle timing ............................................. 8-9
Branch and exchange cycle timing ............................................. 8-10
Thumb branch, link and exchange cycle timing ......................... 8-11
Data operation cycle timing ........................................................ 8-12
MRS cycle timing ........................................................................ 8-14
MSR cycle timing ........................................................................ 8-15
MUL and MLA cycle timing ......................................................... 8-17
MULS and MLAS cycle timing .................................................... 8-17
SMULL, UMULL, SMLAL, and UMLAL cycle timing ................... 8-18
SMULLS, UMULLS, SMLALS, and UMLALS cycle timing ......... 8-18
SMULxy, SMLAxy, SMULWy, and SMLAWy cycle timing ......... 8-19
SMLALxy cycle timing ................................................................ 8-19
QADD, QDADD, QSUB, and QDSUB cycle timing .................... 8-20
Load register operation cycle timing ........................................... 8-23
Cycle timing for load operations resulting in interlocks .............. 8-24
Example sequence LDRB, NOP and ADD cycle timing ............. 8-24
Example sequence LDRB and STMIA cycle timing ................... 8-25
Store register operation cycle timing .......................................... 8-26
LDM cycle timing ........................................................................ 8-28
STM cycle timing ........................................................................ 8-30
Data swap cycle timing ............................................................... 8-33
PLD operation cycle timing ......................................................... 8-35
Exception entry cycle timing ....................................................... 8-36
Coprocessor data operation cycle timing ................................... 8-37
Load coprocessor register cycle timing ...................................... 8-38
Store coprocessor register cycle timing ..................................... 8-40
MRC instruction cycle timing ...................................................... 8-42
MCR instruction cycle timing ...................................................... 8-43
ARM DDI 0165B
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