SAM9261 Atmel Corporation, SAM9261 Datasheet - Page 100
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SAM9261
Manufacturer Part Number
SAM9261
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9260.pdf
(290 pages)
2.SAM9261.pdf
(248 pages)
3.SAM9261.pdf
(749 pages)
4.SAM9261.pdf
(44 pages)
5.SAM9261.pdf
(1274 pages)
6.SAM9261.pdf
(43 pages)
Specifications of SAM9261
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
240 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
1
Uart
4
Ssc
3
Sd / Emmc
1
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
160
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.08 to 1.32
Fpu
No
Mpu / Mmu
No/Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9260 PDF datasheet
- SAM9261 PDF datasheet #2
- SAM9261 PDF datasheet #3
- SAM9261 PDF datasheet #4
- SAM9261 PDF datasheet #5
- SAM9261 PDF datasheet #6
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- Download datasheet (5Mb)
Memory Interface
4.10
4-24
Data interface cycle types
The ARM9E-S data interface is pipelined, and so the address class signals and the
memory request signals are broadcast in the bus cycle ahead of the bus cycle to which
they refer. This gives the maximum time for a memory controller to decode the address,
and respond to the access request.
A single memory cycle is shown in Figure 4-8.
The ARM9E-S data interface can perform four different types of memory cycle. These
are indicated by the state of the DnMREQ and DSEQ signals. Memory cycle types are
encoded on the DnMREQ and DSEQ signals as shown in Table 4-15.
DnMREQ
0
0
1
1
Copyright © 2000 ARM Limited. All rights reserved.
CLK
DnMREQ,
DSEQ,
DMORE
Address class
signals
WDATA[31:0]
(Write)
RDATA[31:0]
(Read)
DSEQ
0
1
0
1
Cycle type
N cycle
S cycle
I cycle
C cycle
Cycle type
Address
Description
Nonsequential cycle
Sequential cycle
Internal cycle
Coprocessor register transfer cycle
Figure 4-8 Simple memory cycle
Bus cycle
Write data
Read data
Table 4-15 Cycle types
ARM DDI 0165B
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