SAM9261 Atmel Corporation, SAM9261 Datasheet - Page 222
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SAM9261
Manufacturer Part Number
SAM9261
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9260.pdf
(290 pages)
2.SAM9261.pdf
(248 pages)
3.SAM9261.pdf
(749 pages)
4.SAM9261.pdf
(44 pages)
5.SAM9261.pdf
(1274 pages)
6.SAM9261.pdf
(43 pages)
Specifications of SAM9261
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
240 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
1
Uart
4
Ssc
3
Sd / Emmc
1
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
160
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.08 to 1.32
Fpu
No
Mpu / Mmu
No/Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9260 PDF datasheet
- SAM9261 PDF datasheet #2
- SAM9261 PDF datasheet #3
- SAM9261 PDF datasheet #4
- SAM9261 PDF datasheet #5
- SAM9261 PDF datasheet #6
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- Download datasheet (5Mb)
Signal Descriptions
A.1
A-2
Clock interface signals
The clock interface signals are given in Table A-1.
Name
CLK
System clock
CLKEN
Wait-state control
CORECLKENOUT
CORECLKENIN
Copyright © 2000 ARM Limited. All rights reserved.
Direction
Input
Input
Output
Input
Description
This clock times all operations in the ARM9E-S
processor. All outputs change from the rising edge
and all inputs are sampled on the rising edge. The
clock can be stretched in either phase. Synchronous
wait states can be added using the CLKEN signal.
Through the use of the DBGTCKEN signal, this
clock also times debug operations.
ARM9E-S can be stalled for integer clock cycles by
driving CLKEN LOW. This signal must be held
HIGH at all other times.
The principal state advance signal for the ARM9E-S
core. This output must be connected directly to the
CORECLKENIN input for correct operation. This
signal has been exported from the core to ease buffer
tree insertion from the CORECLKENIN input. You
must take care when loading and routing the
CORECLKENOUT to CORECLKENIN
connection.
This input must be connected to the
CORECLKENOUT output.
Table A-1 Clock interface signals
ARM DDI 0165B
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