SAM9261 Atmel Corporation, SAM9261 Datasheet - Page 147

• Manufacturer Part Number: SAM9261
• Manufacturer: Atmel Corporation

Specifications of SAM9261

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Ssc: 3
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 160
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

7.5
7.5.1
ARM DDI 0165B
Debug interface signals
Entry into debug state on breakpoint
Breakpointed instruction
DBGIEBKPT
INSTR[31:0]
DBGACK
IA[31:1]
CLK
There are four primary external signals associated with the debug interface:
•
•
An instruction being fetched from memory is sampled at the end of a cycle. To apply a
breakpoint to that instruction, the breakpoint signal must be asserted by the end of the
same cycle. This is shown in Figure 7-4.
You can build external logic, such as additional breakpoint comparators, to extend the
breakpoint functionality of the EmbeddedICE-RT logic. You must apply their output to
the DBGIEBKPT input. This signal is ORed with the internally-generated Breakpoint
signal before being applied to the ARM9E-S core control logic.
The timing of the DBGIEBKPT input makes it unlikely that data-dependent external
breakpoints are possible.
F1
DBGIEBKPT, DBGDEWPT, and EDBGRQ are system requests for the
ARM9E-S to enter debug state
DBGACK is used by the ARM9E-S to flag back to the system that it is in debug
state.
Note
1
Copyright © 2000 ARM Limited. All rights reserved.
D1
F2
2
E1
D2
FB
B
M1
E2
DB
F3
3
Ddebug
(EB)
(D3)
(F4)
W1
M2
Debug Interface and EmbeddedICE-RT
4
Edebug1
Figure 7-4 Breakpoint timing
(MB)
(D4)
(E3)
W2
Edebug2
(WB)
(M3)
(E4)
7-9