SAM9261 Atmel Corporation, SAM9261 Datasheet - Page 265
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SAM9261
Manufacturer Part Number
SAM9261
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9260.pdf
(290 pages)
2.SAM9261.pdf
(248 pages)
3.SAM9261.pdf
(749 pages)
4.SAM9261.pdf
(44 pages)
5.SAM9261.pdf
(1274 pages)
6.SAM9261.pdf
(43 pages)
Specifications of SAM9261
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
240 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
1
Uart
4
Ssc
3
Sd / Emmc
1
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
160
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.08 to 1.32
Fpu
No
Mpu / Mmu
No/Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9260 PDF datasheet
- SAM9261 PDF datasheet #2
- SAM9261 PDF datasheet #3
- SAM9261 PDF datasheet #4
- SAM9261 PDF datasheet #5
- SAM9261 PDF datasheet #6
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C.8.3
C.8.4
ARM DDI 0165B
Watchpoint with another exception
Watchpoint and breakpoint
If a watchpointed access also has a Data Abort returned, the ARM9E-S enters debug
state in Abort mode. Entry into debug is held off until the core changes into Abort mode,
and has fetched the instruction from the abort vector.
A similar sequence follows when an interrupt, or any other exception, occurs during a
watchpointed memory access. The ARM9E-S enters debug state in the mode of the
exception. The debugger must check to see if an exception has occurred by examining
the current and previous mode (in the CPSR and SPSR), and the value of the PC. When
an exception has taken place, you must be given the choice of servicing the exception
before debugging.
For example, suppose that an abort has occurred on a watchpointed access and ten
instructions have been executed in debug state. You can use the following sequence to
return to program execution:
0 EAFFFFF1; B -15 addresses (two’s complement)
1 E1A00000; NOP (MOV R0, R0), SYSSPEED bit is set
This code forces a branch back to the abort vector, causing the instruction at that
location to be refetched and executed.
After the abort service routine, the instruction that caused the abort and watchpoint is
refetched and executed. This triggers the watchpoint again, and the ARM9E-S reenters
debug state.
It is possible to have a watchpoint and breakpoint condition occurring simultaneously.
This can happen when an instruction causes a watchpoint, and the following instruction
has been breakpointed. You must perform the same calculation as for Breakpoints on
page C-24 to determine where to resume. In this case, it is at the breakpoint instruction,
because this has not been executed.
Note
Copyright © 2000 ARM Limited. All rights reserved.
Debug in depth
C-25
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