SAM9261 Atmel Corporation, SAM9261 Datasheet - Page 187
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SAM9261
Manufacturer Part Number
SAM9261
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9260.pdf
(290 pages)
2.SAM9261.pdf
(248 pages)
3.SAM9261.pdf
(749 pages)
4.SAM9261.pdf
(44 pages)
5.SAM9261.pdf
(1274 pages)
6.SAM9261.pdf
(43 pages)
Specifications of SAM9261
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
240 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
1
Uart
4
Ssc
3
Sd / Emmc
1
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
160
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.08 to 1.32
Fpu
No
Mpu / Mmu
No/Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9260 PDF datasheet
- SAM9261 PDF datasheet #2
- SAM9261 PDF datasheet #3
- SAM9261 PDF datasheet #4
- SAM9261 PDF datasheet #5
- SAM9261 PDF datasheet #6
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- Download datasheet (5Mb)
8.14
8.14.1
ARM DDI 0165B
Load multiple registers
Interlocks
A load multiple (
registers transferred and whether the PC is in the list of registers transferred.
1.
2.
When a Data Abort occurs, the instruction continues to completion. The ARM9E-S
prevents all register writing after the abort. The ARM9E-S restores the modified base
pointer (which the load activity before the abort occurred might have overwritten).
When the PC is in the list of registers to be loaded, the ARM9E-S invalidates the current
contents of the instruction pipeline. The PC is always the last register to be loaded, so
an abort at any point prevents the PC from being overwritten.
LDM
POP{Rlist, PC}
An
last data value transferred. This is similar to the interlock cases present with a single
word register load. There is an exception to this case for a single-word
to the presence of an idle cycle at the end of a single-word
exists.
For example, the following sequence incurs a single-cycle interlock:
LDMIA r0, {r1-r2}
ADD
The following sequence incurs a single-cycle interlock:
LDMIA r0, {r1-r2}
STR
The following sequence does not incur an interlock:
LDMIA r0, {r1}
STR
LDM
with
During the first cycle, the ARM9E-S calculates the address of the first word to be
During the second and subsequent cycles, ARM9E-S reads the data requested in
transferred, while performing an instruction prefetch.
the previous cycle and calculates the address of the next word to be transferred.
The new value for the base register is calculated.
r3, r2, r4
r2, [r3]
r1, [r2]
Note
Copyright © 2000 ARM Limited. All rights reserved.
instruction can cause an interlock if a following instruction is dependent on the
destination = PC
LDM
equates to an
) takes several cycles to execute, depending on the number of
cannot be executed in Thumb state. However,
LDM
with
destination = PC
LDM
, no interlock condition
.
Instruction Cycle Times
LDM
where, due
8-27
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