SAM9261 Atmel Corporation, SAM9261 Datasheet - Page 120

• Manufacturer Part Number: SAM9261
• Manufacturer: Atmel Corporation

Specifications of SAM9261

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Ssc: 3
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 160
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

ARM9E-S Coprocessor Interface
6.2
6-4
Coproc CPDOUT[31:0]
Coproc CPDIN[31:0]
LDC/STC
ARM processor pipeline
LATECANCEL
INSTR[31:0]
CHSD[1:0]
CHSE[1:0]
DnMREQ
DA[31:0]
InMREQ
DMORE
PASS
CLK
STC
LDC
shown in Figure 6-1, four words of data are transferred.
The number of words transferred is determined by how the coprocessor drives the
CHSD[1:0] and CHSE[1:0] buses. In the example ARM9E-S
As with all other instructions, the ARM9E-S processor core performs the main decode
using the rising edge of the clock during the Decode stage. From this, the core commits
to executing the instruction, and so performs an instruction fetch. The coprocessor
instruction pipeline keeps in step with the ARM9E-S by monitoring InMREQ.
Copyright © 2000 ARM Limited. All rights reserved.
Figure 6-1 ARM9E-S LDC/STC cycle timing
LDC/STC
ARM DDI 0165B
cycle timing