SAM3N4A Atmel Corporation, SAM3N4A Datasheet - Page 95

• Manufacturer Part Number: SAM3N4A
• Manufacturer: Atmel Corporation

Specifications of SAM3N4A

• Flash (kbytes): 256 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 48 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 79
• Ext Interrupts: 79
• Quadrature Decoder Channels: 2
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Twi (i2c): 2
• Uart: 3
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 24
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

10.12.5
10.12.5.1
10.12.5.2
10.12.5.3
11011A–ATARM–04-Oct-10
LDR, PC-relative
Syntax
Operation
Restrictions
Load register from memory.
where:
type
cond
Rt
Rt2
label
LDR loads a register with a value from a PC-relative memory address. The memory address is
specified by a label or by an offset from the PC.
The value to load or store can be a byte, halfword, or word. For load instructions, bytes and half-
words can either be signed or unsigned. See
label must be within a limited range of the current instruction.
offsets between label and the PC.
Table 10-19. Offset ranges
You might have to use the .W suffix to get the maximum offset range. See
selection” on page
In these instructions:
When Rt is PC in a word load instruction:
Instruction type
Word, halfword, signed halfword, byte, signed
byte
Two words
• Rt can be SP or PC only for word loads
• Rt2 must not be SP and must not be PC
• Rt must be different from Rt2.
LDR{type}{cond} Rt, label
LDRD{cond} Rt, Rt2, label
B
SB
H
SH
-
is one of:
unsigned byte, zero extend to 32 bits.
signed byte, sign extend to 32 bits.
unsigned halfword, zero extend to 32 bits.
signed halfword, sign extend to 32 bits.
omit, for word.
is an optional condition code, see
is the register to load or store.
is the second register to load or store.
is a PC-relative expression. See
86.
“Address alignment” on page
; Load two words
Offset range
− 4095 to 4095
− 1020 to 1020
“PC-relative expressions” on page
“Conditional execution” on page
Table 10-19
83.
shows the possible
“Instruction width
84.
SAM3N
84.
95