SAM3N4A Atmel Corporation, SAM3N4A Datasheet - Page 346

• Manufacturer Part Number: SAM3N4A
• Manufacturer: Atmel Corporation

Specifications of SAM3N4A

• Flash (kbytes): 256 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 48 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 79
• Ext Interrupts: 79
• Quadrature Decoder Channels: 2
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Twi (i2c): 2
• Uart: 3
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 24
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

24.11 Clock Failure Detector
The clock failure detector allows to monitor the 3 to 20 MHz Crystal or Ceramic Resonator-
based oscillator and to detect an eventual defect of this oscillator (for example if the crystal is
unconnected).
The clock failure detector can be enabled or disabled by means of the CFDEN bit in the PMC
Clock Generator Main Oscillator Register (CKGR_MOR). After reset, the detector is disabled.
However, if the 3 to 20 MHz Crystal or Ceramic Resonator-based Oscillator is disabled, the
clock failure detector is disabled too.
A failure is detected by means of a counter incrementing on the 3 to 20 MHzCrystal oscillator or
Ceramic Resonator-based oscillator clock edge and timing logic clocked on the slow clock RC
oscillator controlling the counter. The counter is cleared when the slow clock RC oscillator signal
is low and enabled when the slow clock RC oscillator is high. Thus the failure detection time is 1
slow clock RC oscillator clock period. If, during the high level period of slow clock RC oscillator,
less than 8 fast crystal clock periods have been counted, then a failure is declared.
If a failure of the 3 to 20 MHz Crystal or Ceramic Resonator-based oscillator clock is detected,
the CFDEV flag is set in the PMC Status Register (PMC_SR), and can generate an interrupt if it
is not masked. The interrupt remains active until a read operation in the PMC_SR register. The
user can know the status of the clock failure detector at any time by reading the CFDS bit in the
PMC_SR register.
If the 3 to 20 MHz Crystal or Ceramic Resonator-based oscillator clock is selected as the source
clock of MAINCK (MOSCSEL = 1), and if the Master Clock Source is PLLCK (CSS = 2), then a
clock failure detection switches automatically the Master Clock on MAINCK. Then whatever the
PMC configuration is, a clock failure detection switches automatically MAINCK on the 4/8/12
MHz Fast RC Oscillator clock. If the Fast RC oscillator is disabled when a clock failure detection
occurs, it is automatically re-enabled by the clock failure detection mechanism.
It takes 2 slow clock RC oscillator cycles to detect and switch from the 3 to 20 MHz Crystal or
Ceramic Resonator-based oscillator to the 4/8/12 MHz Fast RC Oscillator if the Master Clock
Source is Main Clock or 3 slow clock RC oscillator cycles if the Master Clock Source is PLL.
The user can know the status of the fault output at any time by reading the
bit in the
FOS
PMC_SR register.
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11011A–ATARM–04-Oct-10