SAM3N4A Atmel Corporation, SAM3N4A Datasheet - Page 57

• Manufacturer Part Number: SAM3N4A
• Manufacturer: Atmel Corporation

Specifications of SAM3N4A

• Flash (kbytes): 256 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 48 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 79
• Ext Interrupts: 79
• Quadrature Decoder Channels: 2
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Twi (i2c): 2
• Uart: 3
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 24
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

10.5.3
10.5.3.1
11011A–ATARM–04-Oct-10
Behavior of memory accesses
Additional memory access constraints for shared memory
< Means that accesses are observed in program order, that is, A1 is always observed before A2.
The behavior of accesses to each region in the memory map is:
Table 10-4.
1.
The Code, SRAM, and external RAM regions can hold programs. However, ARM recommends
that programs always use the Code region. This is because the processor has separate buses
that enable instruction fetches and data accesses to occur simultaneously.
When a system includes shared memory, some memory regions have additional access con-
straints, and some regions are subdivided, as
Table 10-5.
Address
range
0x00000000-
0x1FFFFFFF
0x20000000-
0x3FFFFFFF
0x40000000-
0x5FFFFFFF
0x60000000-
0x9FFFFFFF
0xA0000000-
0xDFFFFFFF
0xE0000000-
0xE00FFFFF
0xE0100000-
0xFFFFFFFF
Address range
0x00000000-
0x1FFFFFFF
0x20000000-
0x3FFFFFFF
0x40000000-
0x5FFFFFFF
0x60000000-
0x7FFFFFFF
0x80000000-
0x9FFFFFFF
See
“Memory regions, types and attributes” on page 55
Memory access behavior
Memory region share ability policies
Memory
region
Code
SRAM
Peripheral
External
RAM
External
device
Private
Peripheral
Bus
Reserved
Memory region
Code
SRAM
Peripheral
External RAM
Memory
type
Normal
Normal
Device
Normal
Device
Strongly-
ordered
Device
(2)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
XN
-
-
XN
-
XN
XN
XN
Memory type
Normal
Normal
Device
Normal
Table 10-5
Description
Executable region for program code. You can also put
data here.
Executable region for data. You can also put code
here.
This region includes bit band and bit band alias areas,
see
This region includes bit band and bit band alias areas,
see
Executable region for data.
External Device memory
This region includes the NVIC, System timer, and
system control block.
Reserved
Table 10-6 on page
Table 10-6 on page
(1)
(1)
(1)
(1)
shows:
for more information.
Shareability
-
-
-
-
59.
59.
WBWA
WT
SAM3N
(2)
(2)
57