SAM3N4A Atmel Corporation, SAM3N4A Datasheet - Page 469

• Manufacturer Part Number: SAM3N4A
• Manufacturer: Atmel Corporation

Specifications of SAM3N4A

• Flash (kbytes): 256 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 48 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 79
• Ext Interrupts: 79
• Quadrature Decoder Channels: 2
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Twi (i2c): 2
• Uart: 3
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 24
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

Figure 28-6. Master Write with One Data Byte
Figure 28-7. Master Write with Multiple Data Bytes
11011A–ATARM–04-Oct-10
11011A–ATARM–04-Oct-10
TXCOMP
TXRDY
TWCK
TWD
Write THR (Data n)
S
DADR
After a Master Write transfer, the Serial Clock line is stretched (tied low) while no new data is
written in the TWI_THR or until a STOP command is performed.
See
TXCOMP
TXRDY
W
Figure
TWD
Write THR (DATA)
A
S
28-6,
STOP Command sent (write in TWI_CR)
DATA n
Figure
DADR
28-7, and
A
W
Figure
Write THR (Data n+1)
A
28-8.
DATA
DATA n+1
STOP command performed
(by writing in the TWI_CR)
A
Write THR (Data n+2)
Last data sent
P
A
DATA n+2
SAM3N
SAM3N
A
P
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