SAM3N4A Atmel Corporation, SAM3N4A Datasheet - Page 441

• Manufacturer Part Number: SAM3N4A
• Manufacturer: Atmel Corporation

Specifications of SAM3N4A

• Flash (kbytes): 256 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 48 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 79
• Ext Interrupts: 79
• Quadrature Decoder Channels: 2
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Twi (i2c): 2
• Uart: 3
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 24
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

Figure 27-10. Chip Select Decoding Application Block Diagram: Single Master/Multiple Slave Implementation
27.7.3.8
11011A–ATARM–04-Oct-10
11011A–ATARM–04-Oct-10
SPI Master
Peripheral Deselection without PDC
NPCS0
NPCS1
NPCS2
NPCS3
SPCK
MISO
MOSI
If the CSAAT bit is used, with or without the PDC, the Mode Fault detection for NPCS0 line must
be disabled. This is not needed for all other chip select lines since Mode Fault Detection is only
on NPCS0.
During a transfer of more than one data on a Chip Select without the PDC, the SPI_TDR is
loaded by the processor, the flag TDRE rises as soon as the content of the SPI_TDR is trans-
ferred into the internal shift register. When this flag is detected high, the SPI_TDR can be
reloaded. If this reload by the processor occurs before the end of the current transfer and if the
next transfer is performed on the same chip select as the current transfer, the Chip Select is not
de-asserted between the two transfers. But depending on the application software handling the
SPI status register flags (by interrupt or polling method) or servicing other interrupts or other
tasks, the processor may not reload the SPI_TDR in time to keep the chip select active (low). A
null Delay Between Consecutive Transfer (DLYBCT) value in the SPI_CSR register, will give
even less time for the processor to reload the SPI_TDR. With some SPI slave peripherals,
requiring the chip select line to remain active (low) during a full set of transfers might lead to
communication errors.
To facilitate interfacing with such devices, the Chip Select Register [CSR0...CSR3] can be pro-
grammed with the CSAAT bit (Chip Select Active After Transfer) at 1. This allows the chip select
lines to remain in their current state (low = active) until transfer to another chip select is required.
Even if the SPI_TDR is not reloaded the chip select will remain active. To have the chip select
line to raise at the end of the transfer the Last transfer Bit (LASTXFER) in the SPI_MR register
must be set at 1 before writing the last data to transmit into the SPI_TDR.
1-of-n Decoder/Demultiplexer
SPCK
Slave 0
MISO MOSI
NSS
SPCK MISO MOSI
Slave 1
NSS
SPCK MISO MOSI
Slave 14
NSS
SAM3N
SAM3N
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