SAM3N4A Atmel Corporation, SAM3N4A Datasheet - Page 682

• Manufacturer Part Number: SAM3N4A
• Manufacturer: Atmel Corporation

Specifications of SAM3N4A

• Flash (kbytes): 256 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 48 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 79
• Ext Interrupts: 79
• Quadrature Decoder Channels: 2
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Twi (i2c): 2
• Uart: 3
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 24
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

34.6
34.6.1
34.6.2
34.6.3
Figure 34-2. Internal trigger
Figure 34-3. External trigger
682
bytes in FIFO
bytes in FIFO
DACC_CDR
DACC_CDR
conversion
conversion
Number of
Number of
External
Internal
TXRDY
TXRDY
trigger
trigger
DACC
DACC
write
write
Functional Description
SAM3N
Digital-to-analog Conversion
Conversion Results
Conversion Triggers
0
data1
0
1
data2
data1 data2 data3 data4
2
1
data3
CLKDIV/2
3 2
2
data1
data4
3
The DAC uses the master clock (MCK) to perform conversions.
Once a conversion has started, the DAC will take a setup time to provide the analog result on
the analog output.
Refer to the product electrical characteristics for more information.
When a conversion is completed, the resulting analog value is available at the DAC channel
output.
In internal trigger mode, conversion starts as soon as the DACC is enabled, data is written in the
DACC Conversion Data Register
internal trigger frequency is configurable through the CLKDIV field of the
and must not be above the maximum frequency allowed by the DAC.
In external trigger mode, the conversion waits for a rising edge event on the selected trigger to
begin (see
Warning: Disabling the external trigger mode will automatically set the DACC in internal trigger
mode.
3
data5
4
4
data1
data2
Figure
CLKDIV
3
34-3).
data3
3
2
data2
data4
and an internal trigger event occurs (see
CLKDIV
1
data5
2
data3
CLKDIV
1
0
DACC Mode Register
data4
11011A–ATARM–04-Oct-10
Figure
34-2). The
0