SAM3N4A Atmel Corporation, SAM3N4A Datasheet - Page 102

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SAM3N4A

Manufacturer Part Number
SAM3N4A
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM3N4A

Flash (kbytes)
256 Kbytes
Pin Count
48
Max. Operating Frequency
48 MHz
Cpu
Cortex-M3
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Quadrature Decoder Channels
2
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
2
Uart
3
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
24
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
6
Output Compare Channels
6
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
10.12.9
10.12.9.1
10.12.9.2
10.12.9.3
10.12.9.4
102
CLREX
SAM3N
CLREX
Syntax
Operation
Condition flags
Examples
Clear Exclusive.
where:
cond
Use CLREX to make the next STREX, STREXB, or STREXH instruction write 1 to its destination
register and fail to perform the store. It is useful in exception handler code to force the failure of
the store exclusive if the exception occurs between a load exclusive instruction and the match-
ing store exclusive instruction in a synchronization operation.
See
These instructions do not change the flags.
CLREX{cond}
“Synchronization primitives” on page 61
is an optional condition code, see
for more information.
“Conditional execution” on page
11011A–ATARM–04-Oct-10
84.

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