M55800A Atmel Corporation, M55800A Datasheet - Page 95
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M55800A
Manufacturer Part Number
M55800A
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.M40800.pdf
(153 pages)
3.M55800A.pdf
(29 pages)
4.M55800A.pdf
(256 pages)
5.M55800A.pdf
(28 pages)
Specifications of M55800A
Flash (kbytes)
0 Kbytes
Pin Count
176
Max. Operating Frequency
33 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
58
Ext Interrupts
58
Usb Speed
No
Usb Interface
No
Spi
1
Uart
3
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
72
Resistive Touch Screen
No
Dac Channels
1
Dac Resolution (bits)
10
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
8
Self Program Memory
NO
External Bus Interface
1
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.3/5.0
Fpu
No
Mpu / Mmu
no / no
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- M40800 PDF datasheet
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14.1.4
Name:
Access:
Reset Value:
Offset:
• WDOVF: Watchdog Overflow (Code Label WD_WDOVF)
0 = No watchdog overflow.
1 = A watchdog overflow has occurred since the last restart of the watchdog counter or since internal or external reset.
14.1.5
To enable the Watchdog Timer, the sequence is as follows:
1745F–ATARM–06-Sep-07
1. Disable the Watchdog by clearing the bit WDEN:
2. Initialize the WD Clock Mode Register:
3. Write 0x373C to WD_CMR
4. Restart the timer:
5. Enable the watchdog:
Write 0x2340 to WD_OMR
This step is unnecessary if the WD is already disabled (reset state).
(HPCV = 15 and WDCLKS = MCK/8)
Write 0xC071 to WD_CR
Write 0x2345 to WD_OMR (interrupt enabled)
31
23
15
–
–
–
7
–
WD Status Register
WD Enabling Sequence
30
22
14
WD_SR
Read-only
0x0
0x0C
–
–
–
6
–
29
21
13
–
–
–
5
–
28
20
12
–
–
–
4
–
27
19
11
–
–
–
3
–
26
18
10
–
–
–
–
2
AT91M5880A
25
17
–
–
–
–
9
1
WDOVF
24
16
–
–
–
8
0
95
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