M55800A Atmel Corporation, M55800A Datasheet - Page 200

• Manufacturer Part Number: M55800A
• Manufacturer: Atmel Corporation

Specifications of M55800A

• Flash (kbytes): 0 Kbytes
• Pin Count: 176
• Max. Operating Frequency: 33 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 58
• Ext Interrupts: 58
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Uart: 3
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 72
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3/5.0
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

20.7.2
Register Name:
Access Type:
Reset State:
Offset:
• MSTR: Master/Slave Mode (Code Label SP_MSTR)
0 = SPI is in Slave mode.
1 = SPI is in Master mode.
MSTR configures the SPI Interface for either master or slave mode operation.
• PS: Peripheral Select
• PCSDEC: Chip Select Decode (Code Label SP_PCSDEC)
0 = The chip selects are directly connected to a peripheral device.
1 = The four chip select lines are connected to a 4- to 16-bit decoder.
When PCSDEC equals one, up to 16 Chip Select signals can be generated with the four lines using an external 4- to 16-bit
decoder.
The Chip Select Registers define the characteristics of the 16 chip selects according to the following rules:
Note:
• MCK32: Clock Selection (Code Label SP_DIV32)
0 = SPI Master Clock equals MCK.
1 = SPI Master Clock equals MCK/32.
200
PS
0
1
LLB
SP_CSR0defines peripheral chip select signals 0 to 3.
SP_CSR1defines peripheral chip select signals 4 to 7.
SP_CSR2defines peripheral chip select signals 8 to 11.
SP_CSR3defines peripheral chip select signals 12 to 15
31
23
15
–
–
7
1. The 16th state corresponds to a state in which all chip selects are inactive. This allows a different clock configuration to be
AT91M5880A
SPI Mode Register
defined by each chip select register.
SP_MR
Read/Write
0
0x04
30
22
14
–
–
6
–
Selected PS
Fixed Peripheral Select
Variable Peripheral Select
29
21
13
–
–
5
–
28
20
12
–
–
4
–
DLYBCS
(1)
.
MCK32
27
19
11
–
3
Code Label: SP_PS
SP_PS_FIXED
SP_PS_VARIABLE
PCSDEC
26
18
10
–
2
PCS
PS
25
17
–
9
1
1745F–ATARM–06-Sep-07
MSTR
24
16
8
–
0