M55800A Atmel Corporation, M55800A Datasheet - Page 192

• Manufacturer Part Number: M55800A
• Manufacturer: Atmel Corporation

Specifications of M55800A

• Flash (kbytes): 0 Kbytes
• Pin Count: 176
• Max. Operating Frequency: 33 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 58
• Ext Interrupts: 58
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Uart: 3
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 72
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3/5.0
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

20.2.2
20.2.3
20.2.4
192
AT91M5880A
Variable Peripheral Select
Chip Selects
Mode Fault Detection
Variable Peripheral Select is activated by setting bit PS to one. The PCS field in SP_TDR
(Transmit Data Register) is used to select the destination peripheral. The data transfer charac-
teristics are changed when the selected peripheral changes, according to the associated chip
select register.
The PCS field in the SP_MR has no effect.
This option is only available when the SPI is programmed in master mode.
The Chip Select lines are driven by the SPI only if it is programmed in Master Mode. These lines
are used to select the destination peripheral. The PCSDEC field in SP_MR (Mode Register)
selects 1 to 4 peripherals (PCSDEC = 0) or up to 15 peripherals (PCSDEC = 1).
If Variable Peripheral Select is active, the chip select signals are defined for each transfer in the
PCS field in SP_TDR. Chip select signals can thus be defined independently for each transfer.
If Fixed Peripheral Select is active, Chip Select signals are defined for all transfers by the field
PCS in SP_MR. If a transfer with a new peripheral is necessary, the software must wait until the
current transfer is completed, then change the value of PCS in SP_MR before writing new data
in SP_TDR.
The value on the NPCS pins at the end of each transfer can be read in the SP_RDR (Receive
Data Register).
By default, all NPCS signals are high (equal to one) before and after each transfer.
A mode fault is detected when the SPI is programmed in Master Mode and a low level is driven
by an external master on the NPCS0/NSS signal.
When a mode fault is detected, the MODF bit in the SP_SR is set until the SP_SR is read and
the SPI is disabled until re-enabled by bit SPIEN in the SP_CR (Control Register).
1745F–ATARM–06-Sep-07